linux-kernel - [PATCH v8 09/13] x86/process: Clear hardware feedback history for AMD processors

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Message-ID: <20250218190822.1039982-10-superm1@kernel.org>
Date: Tue, 18 Feb 2025 13:08:18 -0600
From: Mario Limonciello <superm1@...nel.org>
To: Hans de Goede <hdegoede@...hat.com>,
	Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>
Cc: Mario Limonciello <mario.limonciello@....com>,
	Perry Yuan <perry.yuan@....com>,
	Thomas Gleixner <tglx@...utronix.de>,
	Ingo Molnar <mingo@...hat.com>,
	Borislav Petkov <bp@...en8.de>,
	Dave Hansen <dave.hansen@...ux.intel.com>,
	x86@...nel.org (maintainer:X86 ARCHITECTURE (32-BIT AND 64-BIT)),
	"H . Peter Anvin" <hpa@...or.com>,
	Jonathan Corbet <corbet@....net>,
	Huang Rui <ray.huang@....com>,
	"Gautham R . Shenoy" <gautham.shenoy@....com>,
	"Rafael J . Wysocki" <rafael@...nel.org>,
	Viresh Kumar <viresh.kumar@...aro.org>,
	platform-driver-x86@...r.kernel.org (open list:AMD HETERO CORE HARDWARE FEEDBACK DRIVER),
	linux-kernel@...r.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)),
	linux-doc@...r.kernel.org (open list:DOCUMENTATION),
	linux-pm@...r.kernel.org (open list:AMD PSTATE DRIVER)
Subject: [PATCH v8 09/13] x86/process: Clear hardware feedback history for AMD processors

From: Perry Yuan <perry.yuan@....com>

Incorporate a mechanism within the context switching code to reset
the hardware history for AMD processors. Specifically, when a task
is switched in, the class ID was read and reset the hardware workload
classification history of CPU firmware and then it start to trigger
workload classification for the next running thread.

Signed-off-by: Perry Yuan <perry.yuan@....com>
Co-developed-by: Mario Limonciello <mario.limonciello@....com>
Signed-off-by: Mario Limonciello <mario.limonciello@....com>
---
v8:
 * Only for 64 bit
---
 arch/x86/kernel/process_64.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/x86/kernel/process_64.c b/arch/x86/kernel/process_64.c
index 226472332a70d..371e0e8f987fa 100644
--- a/arch/x86/kernel/process_64.c
+++ b/arch/x86/kernel/process_64.c
@@ -709,6 +709,10 @@ __switch_to(struct task_struct *prev_p, struct task_struct *next_p)
 	/* Load the Intel cache allocation PQR MSR. */
 	resctrl_sched_in(next_p);
 
+	/* Reset hw history on AMD CPUs */
+	if (cpu_feature_enabled(X86_FEATURE_AMD_WORKLOAD_CLASS))
+		wrmsrl(AMD_WORKLOAD_HRST, 0x1);
+
 	return prev_p;
 }
 
-- 
2.43.0