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Message-ID: <25e5840d-a9c3-45fa-ae06-e18c387f1efc@quicinc.com>
Date: Tue, 18 Feb 2025 16:57:12 +0530
From: Manikanta Mylavarapu <quic_mmanikan@...cinc.com>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>, <andersson@...nel.org>,
<mturquette@...libre.com>, <sboyd@...nel.org>, <robh@...nel.org>,
<krzk+dt@...nel.org>, <conor+dt@...nel.org>, <konradybcio@...nel.org>,
<catalin.marinas@....com>, <will@...nel.org>, <p.zabel@...gutronix.de>,
<richardcochran@...il.com>, <geert+renesas@...der.be>,
<dmitry.baryshkov@...aro.org>, <arnd@...db.de>,
<nfraprado@...labora.com>, <biju.das.jz@...renesas.com>,
<quic_tdas@...cinc.com>, <ebiggers@...gle.com>, <ardb@...nel.org>,
<ross.burton@....com>, <quic_anusha@...cinc.com>,
<linux-arm-msm@...r.kernel.org>, <linux-clk@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>, <netdev@...r.kernel.org>
CC: <quic_srichara@...cinc.com>, <quic_varada@...cinc.com>
Subject: Re: [PATCH v9 5/6] arm64: dts: qcom: ipq9574: Add nsscc node
On 2/10/2025 11:47 PM, Konrad Dybcio wrote:
> On 7.02.2025 8:39 AM, Manikanta Mylavarapu wrote:
>> From: Devi Priya <quic_devipriy@...cinc.com>
>>
>> Add a node for the nss clock controller found on ipq9574 based devices.
>>
>> Signed-off-by: Devi Priya <quic_devipriy@...cinc.com>
>> Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@...cinc.com>
>> ---
>> Changes in V9:
>> - Rebased on linux-next tip.
>>
>> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 19 +++++++++++++++++++
>> 1 file changed, 19 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> index 942290028972..29008b156a7e 100644
>> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
>> @@ -1193,6 +1193,25 @@ pcie0: pci@...00000 {
>> status = "disabled";
>> };
>>
>> + nsscc: clock-controller@...00000 {
>> + compatible = "qcom,ipq9574-nsscc";
>> + reg = <0x39b00000 0x80000>;
>> + clocks = <&xo_board_clk>,
>> + <&cmn_pll NSS_1200MHZ_CLK>,
>> + <&cmn_pll PPE_353MHZ_CLK>,
>> + <&gcc GPLL0_OUT_AUX>,
>> + <0>,
>> + <0>,
>> + <0>,
>> + <0>,
>> + <0>,
>> + <0>,
>> + <&gcc GCC_NSSCC_CLK>;
>
> This last clock doesn't seem to be used in the driver - is that by design?
Hi Konrad,
Initially, was under the impression that the GCC_NSSCC_CLK will be enabled by the Ethernet driver.
However, that is incorrect and this clock is needed for accessing the NSSCC block itself. Hence restoring this.
I will enable this clock by using the PM APIs (pm_clk_add()) in next version.
Thanks & Regards,
Manikanta.
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