linux-kernel - [PATCH 0/3] Add support for enabling PLLs and add GE3D clock/reset entries

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Message-ID: <20250218114353.406684-1-prabhakar.mahadev-lad.rj@bp.renesas.com>
Date: Tue, 18 Feb 2025 11:43:50 +0000
From: Prabhakar <prabhakar.csengg@...il.com>
To: Geert Uytterhoeven <geert+renesas@...der.be>,
	Michael Turquette <mturquette@...libre.com>,
	Stephen Boyd <sboyd@...nel.org>
Cc: linux-renesas-soc@...r.kernel.org,
	linux-clk@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	Prabhakar <prabhakar.csengg@...il.com>,
	Biju Das <biju.das.jz@...renesas.com>,
	Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: [PATCH 0/3] Add support for enabling PLLs and add GE3D clock/reset entries

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>

Hi All,

This patch series introduces support for enabling PLL clocks in the
RZ/V2H(P) CPG family driver and adds clock and reset entries for the
GE3D module.

Lad Prabhakar (3):
  clk: renesas: rzv2h-cpg: Move PLL access macros to source file
  clk: renesas: rzv2h-cpg: Add support for enabling PLLs
  clk: renesas: r9a09g057: Add clock and reset entries for GE3D

 drivers/clk/renesas/r9a09g057-cpg.c | 14 +++++++
 drivers/clk/renesas/rzv2h-cpg.c     | 61 +++++++++++++++++++++++++++++
 drivers/clk/renesas/rzv2h-cpg.h     |  4 +-
 3 files changed, 76 insertions(+), 3 deletions(-)

-- 
2.43.0