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Message-Id: <20250219140239.1378758-10-m.wilczynski@samsung.com>
Date: Wed, 19 Feb 2025 15:02:27 +0100
From: Michal Wilczynski <m.wilczynski@...sung.com>
To: mturquette@...libre.com, sboyd@...nel.org, robh@...nel.org,
	krzk+dt@...nel.org, conor+dt@...nel.org, drew@...7.com, guoren@...nel.org,
	wefu@...hat.com, jassisinghbrar@...il.com, paul.walmsley@...ive.com,
	palmer@...belt.com, aou@...s.berkeley.edu, frank.binns@...tec.com,
	matt.coster@...tec.com, maarten.lankhorst@...ux.intel.com,
	mripard@...nel.org, tzimmermann@...e.de, airlied@...il.com, simona@...ll.ch,
	ulf.hansson@...aro.org, jszhang@...nel.org, p.zabel@...gutronix.de,
	m.szyprowski@...sung.com
Cc: linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
	dri-devel@...ts.freedesktop.org, linux-pm@...r.kernel.org, Michal Wilczynski
	<m.wilczynski@...sung.com>
Subject: [PATCH v5 09/21] dt-bindings: clock: thead: Add GPU clkgen reset
 property

Add a mandatory reset property for the TH1520 VO clock controller that
handles the GPU clocks. This reset line controls the GPU CLKGEN reset,
which is required for proper GPU clock operation.

The reset property is only required for the "thead,th1520-clk-vo"
compatible, as it specifically handles the GPU-related clocks.

Signed-off-by: Michal Wilczynski <m.wilczynski@...sung.com>
---
 .../bindings/clock/thead,th1520-clk-ap.yaml      | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml b/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml
index 9d058c00ab3d..6ea8202718d0 100644
--- a/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml
+++ b/Documentation/devicetree/bindings/clock/thead,th1520-clk-ap.yaml
@@ -40,6 +40,12 @@ properties:
             (integer PLL) typically running at 792 MHz (FOUTPOSTDIV), with
             a maximum FOUTVCO of 2376 MHz.
 
+  resets:
+    maxItems: 1
+    description:
+      Required for "thead,th1520-clk-vo". This reset line controls the
+      GPU CLKGEN reset which is required for proper GPU clock operation.
+
   "#clock-cells":
     const: 1
     description:
@@ -51,6 +57,16 @@ required:
   - clocks
   - "#clock-cells"
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: thead,th1520-clk-vo
+    then:
+      required:
+        - resets
+
 additionalProperties: false
 
 examples:
-- 
2.34.1


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