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Message-ID: <20250219-sudoku-brewery-196094c5a506@spud>
Date: Wed, 19 Feb 2025 17:39:56 +0000
From: Conor Dooley <conor@...nel.org>
To: linux-riscv@...ts.infradead.org,
Conor Dooley <conor@...nel.org>,
Emil Renner Berthing <kernel@...il.dk>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Sandie Cao <sandie.cao@...pcomputing.io>
Cc: Conor Dooley <conor.dooley@...rochip.com>,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>
Subject: Re: [PATCH] riscv: dts: starfive: fml13v01: enable pcie1
From: Conor Dooley <conor.dooley@...rochip.com>
On Fri, 07 Feb 2025 17:36:18 +0800, Sandie Cao wrote:
> Starfive Soc common defines GPIO28 as pcie1 reset, GPIO21 as pcie1 wakeup;
> But the FML13V01 board uses GPIO21 as pcie1 reset, GPIO28 as pcie1 wakeup;
> redefine pcie1 gpio and enable pcie1 for pcie based Wi-Fi.
>
>
Applied to riscv-dt-for-next, thanks!
[1/1] riscv: dts: starfive: fml13v01: enable pcie1
https://git.kernel.org/conor/c/57b5369f3668
Thanks,
Conor.
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