[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <f0e5efb7-8ea0-a064-21e4-6d7596b1a9ae@oss.qualcomm.com>
Date: Wed, 19 Feb 2025 23:28:47 +0530
From: Krishna Chaitanya Chundru <krishna.chundru@....qualcomm.com>
To: Bjorn Helgaas <helgaas@...nel.org>
Cc: Bjorn Helgaas <bhelgaas@...gle.com>,
Ilpo Järvinen <ilpo.jarvinen@...ux.intel.com>,
Jingoo Han <jingoohan1@...il.com>,
Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof Wilczyński <kw@...ux.com>,
Rob Herring <robh@...nel.org>,
Johannes Berg <johannes@...solutions.net>,
Jeff Johnson <jjohnson@...nel.org>, linux-pci@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org,
mhi@...ts.linux.dev, linux-wireless@...r.kernel.org,
ath11k@...ts.infradead.org, quic_jjohnson@...cinc.com,
quic_pyarlaga@...cinc.com, quic_vbadigan@...cinc.com,
quic_vpernami@...cinc.com, quic_mrana@...cinc.com
Subject: Re: [PATCH 4/8] PCI: dwc: qcom: Update ICC & OPP votes based upon the
requested speed
On 2/19/2025 3:37 AM, Bjorn Helgaas wrote:
> Make subject line match history for this file.
>
> On Mon, Feb 17, 2025 at 12:04:11PM +0530, Krishna Chaitanya Chundru wrote:
>> QCOM PCIe controllers needs to disable ASPM before initiating link
>> re-train. So as part of pre_bw_scale() disable ASPM and as part of
>> post_scale_bus_bw() enable ASPM back.
>
> s/needs/need/
>
> Why does Qcom need to disable ASPM? Is there a PCIe spec restriction
> about this that should be applied to all PCIe host bridges? Or is
> this a Qcom defect?
>
It is QCOM controller issue, PCIe spec doesn't mention to disable ASPM.
>> Update ICC & OPP votes based on the requested speed so that RPMh votes
>> gets updated based on the speed.
>
> s/gets/get/
>
>> Bring out the core logic from qcom_pcie_icc_opp_update() to new function
>> qcom_pcie_set_icc_opp().
>
> This refactoring possibly could be a separate patch to make the meat
> of this change clearer.
>
ack.
- Krishna Chaitanya.
>> +static int qcom_pcie_set_icc_opp(struct qcom_pcie *pcie, int speed, int width)
>> +{
>> + struct dw_pcie *pci = pcie->pci;
>> + unsigned long freq_kbps;
>> + struct dev_pm_opp *opp;
>> + int ret, freq_mbps;
>> +
>> + if (pcie->icc_mem) {
>> + ret = icc_set_bw(pcie->icc_mem, 0,
>> + width * QCOM_PCIE_LINK_SPEED_TO_BW(speed));
>> + if (ret) {
>> + dev_err(pci->dev, "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n",
>> + ret);
>> + }
>> + } else if (pcie->use_pm_opp) {
>> + freq_mbps = pcie_dev_speed_mbps(pcie_link_speed[speed]);
>> + if (freq_mbps < 0)
>> + return -EINVAL;
>> +
>> + freq_kbps = freq_mbps * KILO;
>> + opp = dev_pm_opp_find_freq_exact(pci->dev, freq_kbps * width,
>> + true);
>> + if (!IS_ERR(opp)) {
>> + ret = dev_pm_opp_set_opp(pci->dev, opp);
>> + if (ret)
>> + dev_err(pci->dev, "Failed to set OPP for freq (%lu): %d\n",
>> + freq_kbps * width, ret);
>> + dev_pm_opp_put(opp);
>> + }
>> + }
>> +
>> + return ret;
>
> Looks uninitialized in some paths.
Powered by blists - more mailing lists