linux-kernel - Re: [PATCH 1/2] x86/cpufeatures: Add CPU feature flags for Zhaoxin Hash Engine v2

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Message-ID: <20250219193007.GPZ7YxP3aKjTV08yJo@fat_crate.local>
Date: Wed, 19 Feb 2025 20:30:07 +0100
From: Borislav Petkov <bp@...en8.de>
To: Tony W Wang-oc <TonyWWang-oc@...oxin.com>
Cc: tglx@...utronix.de, mingo@...hat.com, dave.hansen@...ux.intel.com,
	x86@...nel.org, hpa@...or.com, pawan.kumar.gupta@...ux.intel.com,
	jpoimboe@...nel.org, daniel.sneddon@...ux.intel.com,
	perry.yuan@....com, thomas.lendacky@....com, sandipan.das@....com,
	namhyung@...nel.org, acme@...hat.com, xin3.li@...el.com,
	brijesh.singh@....com, linux-kernel@...r.kernel.org,
	herbert@...dor.apana.org.au, davem@...emloft.net,
	linux-crypto@...r.kernel.org, CobeChen@...oxin.com,
	TimGuo@...oxin.com, LeoLiu-oc@...oxin.com, GeorgeXue@...oxin.com
Subject: Re: [PATCH 1/2] x86/cpufeatures: Add CPU feature flags for Zhaoxin
 Hash Engine v2

On Tue, Jan 14, 2025 at 08:13:00PM +0800, Tony W Wang-oc wrote:
> Zhaoxin currently uses CPUID leaf 0xC0000001 instead of VIA/Cyrix/
> Centaur to represent the presence or absence of certain CPU features
> due to company changes. The previously occupied bits in CPUID leaf
> 0xC0000001 remain functional, and the unoccupied bits are used by
> Zhaoxin to represent some new CPU features.
> 
> Zhaoxin CPUs implements the PadLock Hash Engine v2 feature on the
> basis of features supported by CPUID leaf 0xC0000001, which indicates
> that Zhaoxin CPUs support SHA384/SHA512 algorithm hardware instructions.
> 
> Add two Padlock Hash Engine v2 feature flags support in cpufeatures.h
> 
> Signed-off-by: Tony W Wang-oc <TonyWWang-oc@...oxin.com>
> ---
>  arch/x86/include/asm/cpufeatures.h       | 4 +++-
>  tools/arch/x86/include/asm/cpufeatures.h | 4 +++-
>  2 files changed, 6 insertions(+), 2 deletions(-)

I'm assuming this is going through the crypto tree due to patch 2 so for this
one:

Acked-by: Borislav Petkov (AMD) <bp@...en8.de>

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette