linux-kernel - Re: [PATCH v4 5/9] dt-bindings: watchdog: renesas: Document `renesas,syscon-cpg-error-rst` property

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Message-ID: <173999884492.2929715.139176403208414695.robh@kernel.org>
Date: Wed, 19 Feb 2025 15:00:45 -0600
From: "Rob Herring (Arm)" <robh@...nel.org>
To: Prabhakar <prabhakar.csengg@...il.com>
Cc: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Michael Turquette <mturquette@...libre.com>,
	Wolfram Sang <wsa+renesas@...g-engineering.com>,
	Guenter Roeck <linux@...ck-us.net>, devicetree@...r.kernel.org,
	Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
	linux-renesas-soc@...r.kernel.org, linux-watchdog@...r.kernel.org,
	linux-kernel@...r.kernel.org, Biju Das <biju.das.jz@...renesas.com>,
	Conor Dooley <conor+dt@...nel.org>,
	Wim Van Sebroeck <wim@...ux-watchdog.org>,
	linux-clk@...r.kernel.org, Stephen Boyd <sboyd@...nel.org>,
	Geert Uytterhoeven <geert+renesas@...der.be>,
	Magnus Damm <magnus.damm@...il.com>
Subject: Re: [PATCH v4 5/9] dt-bindings: watchdog: renesas: Document
 `renesas,syscon-cpg-error-rst` property


On Mon, 10 Feb 2025 18:49:06 +0000, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> 
> The CPG block in the RZ/V2H(P) and RZ/G3E SoCs includes Error Reset Select
> Registers (`CPG_ERRORRST_SELm`) and Error Reset Registers
> (`CPG_ERROR_RSTm`). The `CPG_ERRORRST_SELm` register must be configured to
> trigger a system reset in response to specific error conditions, while the
> `CPG_ERROR_RSTm` registers store the error interrupt factors that caused
> the system reset.
> 
> For the watchdog IP to trigger a system reset on a watchdog timer
> underflow, the `CPG_ERRORRST_SEL2` and `CPG_ERROR_RST2` registers in the
> CPG block must be configured. For example, setting `BIT(1)` in
> `CPG_ERRORRST_SEL2` allows WDT1 to issue a system reset upon a watchdog
> timer underflow. Similarly, `BIT(1)` in `CPG_ERROR_RST2` indicates whether
> the system reset was caused by a WDT1 underflow. This functionality
> enables the watchdog driver to configure the `CPG_ERRORRST_SEL2` register
> and determine whether the system booted due to a `Power-on Reset` or a
> `Watchdog Reset`.
> 
> To support this operation, add the `renesas,syscon-cpg-error-rst` property
> to the WDT node. This property maps to the `syscon` CPG node, allowing the
> watchdog driver to configure and retrieve the necessary reset information.
> 
> Additionally, this property is marked as required for the RZ/V2H(P) and
> RZ/G3E SoC to ensure future compatibility and is explicitly disallowed
> for other SoCs.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> ---
> Note, this change doesnt break any ABI, as the subsequent driver patch
> handles the case elegantly if the `syscon` node is missing to handle
> backward compatibility.
> 
> v3->v4
> - Updated commit message
> 
> v2->v3
> - No change
> 
> v1->v2
> - Renamed `renesas,r9a09g057-syscon-wdt-errorrst` to `renesas,syscon-cpg-error-rst`
> - Updated commit message
> ---
>  .../bindings/watchdog/renesas,wdt.yaml          | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 

Reviewed-by: Rob Herring (Arm) <robh@...nel.org>