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Message-ID: <Z7ZLB-wZY9wTZSBZ@google.com>
Date: Wed, 19 Feb 2025 13:20:07 -0800
From: Namhyung Kim <namhyung@...nel.org>
To: Samuel Holland <samuel.holland@...ive.com>,
linux-riscv@...ts.infradead.org
Cc: Arnaldo Carvalho de Melo <acme@...hat.com>,
Ian Rogers <irogers@...gle.com>,
Palmer Dabbelt <palmer@...belt.com>,
linux-perf-users@...r.kernel.org,
Mark Rutland <mark.rutland@....com>,
Adrian Hunter <adrian.hunter@...el.com>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
linux-kernel@...r.kernel.org, Jiri Olsa <jolsa@...nel.org>,
Peter Zijlstra <peterz@...radead.org>,
Ingo Molnar <mingo@...hat.com>,
Arnaldo Carvalho de Melo <acme@...nel.org>
Subject: Re: [RESEND PATCH 0/7] perf vendor events riscv: Update SiFive CPU
PMU events
Hello,
On Wed, Feb 12, 2025 at 05:21:33PM -0800, Samuel Holland wrote:
> This series updates the PMU event JSON files to add support for newer
> SiFive CPUs, including those used in the HiFive Premier P550 board.
> Since most changes are incremental, symbolic links are used when a set
> of events is unchanged from the previous CPU series.
>
> I originally sent this series about a year ago[1], but received no
> feedback. The P550 board is now available (and I have tested this series
> on it), so it would be good to get perf support for it upstream.
>
> [1]: https://lore.kernel.org/linux-perf-users/20240509021531.680920-1-samuel.holland@sifive.com/
>
>
> Eric Lin (5):
> perf vendor events riscv: Update SiFive Bullet events
> perf vendor events riscv: Add SiFive Bullet version 0x07 events
> perf vendor events riscv: Add SiFive Bullet version 0x0d events
> perf vendor events riscv: Add SiFive P550 events
> perf vendor events riscv: Add SiFive P650 events
>
> Samuel Holland (2):
> perf vendor events riscv: Rename U74 to Bullet
> perf vendor events riscv: Remove leading zeroes
It'd be nice if anyone in the RISC-V community can review this.
Thanks,
Namhyung
>
> tools/perf/pmu-events/arch/riscv/mapfile.csv | 6 +-
> .../cycle-and-instruction-count.json | 12 +++
> .../arch/riscv/sifive/bullet-07/firmware.json | 1 +
> .../riscv/sifive/bullet-07/instruction.json | 1 +
> .../arch/riscv/sifive/bullet-07/memory.json | 1 +
> .../riscv/sifive/bullet-07/microarch.json | 62 +++++++++++++
> .../riscv/sifive/bullet-07/watchpoint.json | 42 +++++++++
> .../cycle-and-instruction-count.json | 1 +
> .../arch/riscv/sifive/bullet-0d/firmware.json | 1 +
> .../riscv/sifive/bullet-0d/instruction.json | 1 +
> .../arch/riscv/sifive/bullet-0d/memory.json | 1 +
> .../riscv/sifive/bullet-0d/microarch.json | 72 +++++++++++++++
> .../riscv/sifive/bullet-0d/watchpoint.json | 1 +
> .../sifive/{u74 => bullet}/firmware.json | 0
> .../arch/riscv/sifive/bullet/instruction.json | 92 +++++++++++++++++++
> .../arch/riscv/sifive/bullet/memory.json | 32 +++++++
> .../arch/riscv/sifive/bullet/microarch.json | 57 ++++++++++++
> .../arch/riscv/sifive/p550/firmware.json | 1 +
> .../arch/riscv/sifive/p550/instruction.json | 1 +
> .../arch/riscv/sifive/p550/memory.json | 47 ++++++++++
> .../arch/riscv/sifive/p550/microarch.json | 1 +
> .../p650/cycle-and-instruction-count.json | 1 +
> .../arch/riscv/sifive/p650/firmware.json | 1 +
> .../arch/riscv/sifive/p650/instruction.json | 1 +
> .../arch/riscv/sifive/p650/memory.json | 57 ++++++++++++
> .../arch/riscv/sifive/p650/microarch.json | 62 +++++++++++++
> .../arch/riscv/sifive/p650/watchpoint.json | 1 +
> .../arch/riscv/sifive/u74/instructions.json | 92 -------------------
> .../arch/riscv/sifive/u74/memory.json | 32 -------
> .../arch/riscv/sifive/u74/microarch.json | 57 ------------
> 30 files changed, 555 insertions(+), 182 deletions(-)
> create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/cycle-and-instruction-count.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/firmware.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/instruction.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/memory.json
> create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/microarch.json
> create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-07/watchpoint.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/cycle-and-instruction-count.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/firmware.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/instruction.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/memory.json
> create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/microarch.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/watchpoint.json
> rename tools/perf/pmu-events/arch/riscv/sifive/{u74 => bullet}/firmware.json (100%)
> create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/memory.json
> create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet/microarch.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/firmware.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p550/memory.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p550/microarch.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/cycle-and-instruction-count.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/firmware.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/instruction.json
> create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p650/memory.json
> create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/p650/microarch.json
> create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/p650/watchpoint.json
> delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/instructions.json
> delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json
> delete mode 100644 tools/perf/pmu-events/arch/riscv/sifive/u74/microarch.json
>
> --
> 2.47.0
>
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