linux-kernel - Re: [PATCH v2 10/16] drm/msm/dpu: Add handling of LM_6 and LM

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Message-ID: <cf42fa47-eb79-49bc-b526-50173562c44c@quicinc.com>
Date: Wed, 19 Feb 2025 13:28:08 -0800
From: Jessica Zhang <quic_jesszhan@...cinc.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
        Rob Clark
	<robdclark@...il.com>,
        Abhinav Kumar <quic_abhinavk@...cinc.com>,
        "Dmitry
 Baryshkov" <dmitry.baryshkov@...aro.org>,
        Sean Paul <sean@...rly.run>,
        "Marijn Suijten" <marijn.suijten@...ainline.org>,
        David Airlie
	<airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
        Maarten Lankhorst
	<maarten.lankhorst@...ux.intel.com>,
        Maxime Ripard <mripard@...nel.org>,
        Thomas Zimmermann <tzimmermann@...e.de>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>,
        Krishna Manikandan <quic_mkrishn@...cinc.com>,
        Jonathan Marek
	<jonathan@...ek.ca>,
        Kuogee Hsieh <quic_khsieh@...cinc.com>,
        Neil Armstrong
	<neil.armstrong@...aro.org>
CC: <linux-arm-msm@...r.kernel.org>, <dri-devel@...ts.freedesktop.org>,
        <freedreno@...ts.freedesktop.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>,
        Srini Kandagatla
	<srinivas.kandagatla@...aro.org>
Subject: Re: [PATCH v2 10/16] drm/msm/dpu: Add handling of LM_6 and LM_7 bits
 in pending flush mask



On 2/17/2025 8:41 AM, Krzysztof Kozlowski wrote:
> MDSS/MDP v12 comes with new bits in flush registers (e.g.
> MDP_CTL_0_FLUSH) for Layer Mixer 6 and 7.
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>

Reviewed-by: Jessica Zhang <quic_jesszhan@...cinc.com>

> ---
>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 6 ++++++
>   1 file changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> index 0021df38f8662683771abb2cef7794c3209e9413..9d4866509e97c262006e15cf3e02a2f1ca851784 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> @@ -254,6 +254,12 @@ static void dpu_hw_ctl_update_pending_flush_mixer(struct dpu_hw_ctl *ctx,
>   	case LM_5:
>   		ctx->pending_flush_mask |= BIT(20);
>   		break;
> +	case LM_6:
> +		ctx->pending_flush_mask |= BIT(21);
> +		break;
> +	case LM_7:
> +		ctx->pending_flush_mask |= BIT(27);
> +		break;
>   	default:
>   		break;
>   	}
> 
> -- 
> 2.43.0
>