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Message-ID: <a049b7ae-e3b2-4300-81ee-76f677804135@huawei.com>
Date: Wed, 19 Feb 2025 15:40:00 +0800
From: Yongbang Shi <shiyongbang@...wei.com>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
CC: <xinliang.liu@...aro.org>, <tiantao6@...ilicon.com>,
<maarten.lankhorst@...ux.intel.com>, <mripard@...nel.org>,
<tzimmermann@...e.de>, <airlied@...il.com>, <daniel@...ll.ch>,
<kong.kongxinwei@...ilicon.com>, <liangjian010@...wei.com>,
<chenjianmin@...wei.com>, <lidongming5@...wei.com>, <libaihan@...wei.com>,
<shenjian15@...wei.com>, <shaojijie@...wei.com>,
<dri-devel@...ts.freedesktop.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 drm-dp 4/7] drm/hisilicon/hibmc: Add colorbar-cfg: set
color bar cfg
> On Mon, Feb 10, 2025 at 10:49:56PM +0800, Yongbang Shi wrote:
>> From: Baihan Li <libaihan@...wei.com>
>>
>> This is a DP IP controller's feature. It can be used as a debug method
>> which can check DP controller is working good. The colorbar displaying
>> doesn't rely on other IPs work in the chip, like: GPU or DDR (vram) and
>> so on, because colorbar diplaying data is generated by controller itself
>> inside the DP IP.
> You are describing it in a pretty strange manner. Does this sound
> better?
>
> DP controller can support generating a color bar signal over the
> DisplayPort interface. This can be useful to check for possible memory
> or GPU problems, as the signal generator resides completely in the DP
> block. Add debugfs file that controls colorbar generator.
>
> This also requires having corresponding debugfs entry here.
Hi Dmitry,
Thank you for your guidance, I got it.
>> Signed-off-by: Baihan Li <libaihan@...wei.com>
>> Signed-off-by: Yongbang Shi <shiyongbang@...wei.com>
>> ---
>> ChangeLog:
>> v1 -> v2:
>> - add colorbar introduction in commit, suggested by Dmitry Baryshkov.
>> - splittting colorbar and debugfs in different patches, suggested by Dmitry Baryshkov.
>> ---
>> drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c | 43 +++++++++++++++++++++
>> drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h | 29 ++++++++++++++
>> drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h | 2 +
>> 3 files changed, 74 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c
>> index 77f02d5151f7..8adace0befde 100644
>> --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c
>> +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c
>> @@ -226,3 +226,46 @@ int hibmc_dp_mode_set(struct hibmc_dp *dp, struct drm_display_mode *mode)
>>
>> return 0;
>> }
>> +
>> +static const struct hibmc_dp_color_raw g_rgb_raw[] = {
>> + {CBAR_COLOR_BAR, 0x000, 0x000, 0x000},
>> + {CBAR_WHITE, 0xfff, 0xfff, 0xfff},
>> + {CBAR_RED, 0xfff, 0x000, 0x000},
>> + {CBAR_ORANGE, 0xfff, 0x800, 0x000},
>> + {CBAR_YELLOW, 0xfff, 0xfff, 0x000},
>> + {CBAR_GREEN, 0x000, 0xfff, 0x000},
>> + {CBAR_CYAN, 0x000, 0x800, 0x800},
>> + {CBAR_BLUE, 0x000, 0x000, 0xfff},
>> + {CBAR_PURPLE, 0x800, 0x000, 0x800},
>> + {CBAR_BLACK, 0x000, 0x000, 0x000},
>> +};
>> +
>> +void hibmc_dp_set_cbar(struct hibmc_dp *dp, const struct hibmc_dp_cbar_cfg *cfg)
>> +{
>> + struct hibmc_dp_dev *dp_dev = dp->dp_dev;
>> + struct hibmc_dp_color_raw raw_data;
>> +
>> + if (cfg->enable) {
>> + hibmc_dp_reg_write_field(dp_dev, HIBMC_DP_COLOR_BAR_CTRL, BIT(9),
>> + cfg->self_timing);
>> + hibmc_dp_reg_write_field(dp_dev, HIBMC_DP_COLOR_BAR_CTRL, GENMASK(8, 1),
>> + cfg->dynamic_rate);
>> + if (cfg->pattern == CBAR_COLOR_BAR) {
>> + hibmc_dp_reg_write_field(dp_dev, HIBMC_DP_COLOR_BAR_CTRL, BIT(10), 0);
>> + } else {
>> + raw_data = g_rgb_raw[cfg->pattern];
>> + drm_dbg_dp(dp->drm_dev, "r:%x g:%x b:%x\n", raw_data.r_value,
>> + raw_data.g_value, raw_data.b_value);
>> + hibmc_dp_reg_write_field(dp_dev, HIBMC_DP_COLOR_BAR_CTRL, BIT(10), 1);
>> + hibmc_dp_reg_write_field(dp_dev, HIBMC_DP_COLOR_BAR_CTRL, GENMASK(23, 12),
>> + raw_data.r_value);
>> + hibmc_dp_reg_write_field(dp_dev, HIBMC_DP_COLOR_BAR_CTRL1, GENMASK(23, 12),
>> + raw_data.g_value);
>> + hibmc_dp_reg_write_field(dp_dev, HIBMC_DP_COLOR_BAR_CTRL1, GENMASK(11, 0),
>> + raw_data.b_value);
>> + }
>> + }
>> +
>> + hibmc_dp_reg_write_field(dp_dev, HIBMC_DP_COLOR_BAR_CTRL, BIT(0), cfg->enable);
>> + writel(HIBMC_DP_SYNC_EN_MASK, dp_dev->base + HIBMC_DP_TIMING_SYNC_CTRL);
>> +}
>> diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h
>> index 53b6d0beecea..621a0a1d7eb7 100644
>> --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h
>> +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h
>> @@ -14,6 +14,33 @@
>>
>> struct hibmc_dp_dev;
>>
>> +enum hibmc_dp_cbar_pattern {
>> + CBAR_COLOR_BAR,
>> + CBAR_WHITE,
>> + CBAR_RED,
>> + CBAR_ORANGE,
>> + CBAR_YELLOW,
>> + CBAR_GREEN,
>> + CBAR_CYAN,
>> + CBAR_BLUE,
>> + CBAR_PURPLE,
>> + CBAR_BLACK,
>> +};
>> +
>> +struct hibmc_dp_color_raw {
>> + enum hibmc_dp_cbar_pattern pattern;
>> + u32 r_value;
>> + u32 g_value;
>> + u32 b_value;
>> +};
>> +
>> +struct hibmc_dp_cbar_cfg {
>> + bool enable;
>> + bool self_timing;
>> + u8 dynamic_rate; /* 0:static, 1-255(frame):dynamic */
>> + enum hibmc_dp_cbar_pattern pattern;
>> +};
>> +
>> struct hibmc_dp {
>> struct hibmc_dp_dev *dp_dev;
>> struct drm_device *drm_dev;
>> @@ -21,10 +48,12 @@ struct hibmc_dp {
>> struct drm_connector connector;
>> void __iomem *mmio;
>> struct drm_dp_aux aux;
>> + struct hibmc_dp_cbar_cfg cfg;
>> };
>>
>> int hibmc_dp_hw_init(struct hibmc_dp *dp);
>> int hibmc_dp_mode_set(struct hibmc_dp *dp, struct drm_display_mode *mode);
>> void hibmc_dp_display_en(struct hibmc_dp *dp, bool enable);
>> +void hibmc_dp_set_cbar(struct hibmc_dp *dp, const struct hibmc_dp_cbar_cfg *cfg);
>>
>> #endif
>> diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h
>> index f2fa9807d8ab..c43ad6b30c2c 100644
>> --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h
>> +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_reg.h
>> @@ -23,6 +23,8 @@
>> #define HIBMC_DP_VIDEO_MSA1 0x11c
>> #define HIBMC_DP_VIDEO_MSA2 0x120
>> #define HIBMC_DP_VIDEO_HORIZONTAL_SIZE 0X124
>> +#define HIBMC_DP_COLOR_BAR_CTRL 0x260
>> +#define HIBMC_DP_COLOR_BAR_CTRL1 0x264
>> #define HIBMC_DP_TIMING_GEN_CONFIG0 0x26c
>> #define HIBMC_DP_TIMING_GEN_CONFIG2 0x274
>> #define HIBMC_DP_TIMING_GEN_CONFIG3 0x278
>> --
>> 2.33.0
>>
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