linux-kernel - [PATCH 2/7] clk: renesas: r9a09g047: Add clock and reset signals for the TSU IP

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Message-ID: <20250220152640.49010-3-john.madieu.xa@bp.renesas.com>
Date: Thu, 20 Feb 2025 16:26:07 +0100
From: John Madieu <john.madieu.xa@...renesas.com>
To: mturquette@...libre.com,
	magnus.damm@...il.com,
	krzk+dt@...nel.org,
	rui.zhang@...el.com,
	daniel.lezcano@...aro.org,
	sboyd@...nel.org,
	geert+renesas@...der.be,
	lukasz.luba@....com,
	rafael@...nel.org,
	robh@...nel.org,
	p.zabel@...gutronix.de
Cc: biju.das.jz@...renesas.com,
	claudiu.beznea.uj@...renesas.com,
	conor+dt@...nel.org,
	devicetree@...r.kernel.org,
	john.madieu@...il.com,
	linux-kernel@...r.kernel.org,
	linux-renesas-soc@...r.kernel.org,
	linux-clk@...r.kernel.org,
	John Madieu <john.madieu.xa@...renesas.com>
Subject: [PATCH 2/7] clk: renesas: r9a09g047: Add clock and reset signals for the TSU IP

Add required clocks and resets signals for the TSU IP available on the
Renesas RZ/G3E SoC

Signed-off-by: John Madieu <john.madieu.xa@...renesas.com>
---
 drivers/clk/renesas/r9a09g047-cpg.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
index 51fd24c20ed5..ada57964c132 100644
--- a/drivers/clk/renesas/r9a09g047-cpg.c
+++ b/drivers/clk/renesas/r9a09g047-cpg.c
@@ -154,6 +154,8 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
 						BUS_MSTOP(8, BIT(4))),
 	DEF_MOD("sdhi_2_aclk",			CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
 						BUS_MSTOP(8, BIT(4))),
+	DEF_MOD("tsu_1_pclk",			CLK_QEXTAL, 16, 10, 8, 10,
+						BUS_MSTOP(2, BIT(15))),
 };
 
 static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
@@ -177,6 +179,7 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
 	DEF_RST(10, 7, 4, 24),		/* SDHI_0_IXRST */
 	DEF_RST(10, 8, 4, 25),		/* SDHI_1_IXRST */
 	DEF_RST(10, 9, 4, 26),		/* SDHI_2_IXRST */
+	DEF_RST(15, 8, 7, 9),		/* TSU_1_PRESETN */
 };
 
 const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = {
-- 
2.25.1