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Message-ID: <Z7eHeuikvako1Xhh@gourry-fedora-PF4VCD3F>
Date: Thu, 20 Feb 2025 14:50:18 -0500
From: Gregory Price <gourry@...rry.net>
To: Robert Richter <rrichter@....com>
Cc: Alison Schofield <alison.schofield@...el.com>,
Vishal Verma <vishal.l.verma@...el.com>,
Ira Weiny <ira.weiny@...el.com>,
Dan Williams <dan.j.williams@...el.com>,
Jonathan Cameron <Jonathan.Cameron@...wei.com>,
Dave Jiang <dave.jiang@...el.com>,
Davidlohr Bueso <dave@...olabs.net>, linux-cxl@...r.kernel.org,
linux-kernel@...r.kernel.org,
"Fabio M. De Francesco" <fabio.m.de.francesco@...ux.intel.com>,
Terry Bowman <terry.bowman@....com>
Subject: Re: [PATCH v2 11/15] cxl/region: Use the endpoint's SPA range to
check a region
On Tue, Feb 18, 2025 at 02:23:52PM +0100, Robert Richter wrote:
> Endpoints or switches requiring address translation might not be aware
> of the system's interleaving configuration. Then, the configured
> endpoint's address range might not match the expected range. In
> contrast, the SPA range of an endpoint is calculated applying platform
> specific address translation. That range is correct and can be used to
> check a region range.
>
> Adjust the region range check and use the endpoint's SPA range to
> check it.
>
> Signed-off-by: Robert Richter <rrichter@....com>
Explanation could be a little clearer, something like:
Endpoint and switch decoders may have an HPA range that differs from
the memory region's SPA range. Utilize the device's calculated
spa_range instead of its hpa_range to validate the region mapping.
The interleave comments don't seem particularly relevant here unless i'm
missing something.
The content of the patch looks good.
Reviewed-by: Gregory Price <gourry@...rry.net>
> ---
> drivers/cxl/core/region.c | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c
> index 3afcc9ca06ae..2ca24565757a 100644
> --- a/drivers/cxl/core/region.c
> +++ b/drivers/cxl/core/region.c
> @@ -1531,22 +1531,26 @@ static int cxl_port_setup_targets(struct cxl_port *port,
> if (test_bit(CXL_REGION_F_AUTO, &cxlr->flags)) {
> if (cxld->interleave_ways != iw ||
> cxld->interleave_granularity != ig ||
> - cxld->hpa_range.start != p->res->start ||
> - cxld->hpa_range.end != p->res->end ||
> + cxled->spa_range.start != p->res->start ||
> + cxled->spa_range.end != p->res->end ||
> ((cxld->flags & CXL_DECODER_F_ENABLE) == 0)) {
> dev_err(&cxlr->dev,
> "%s:%s %s expected iw: %d ig: %d %pr\n",
> dev_name(port->uport_dev), dev_name(&port->dev),
> __func__, iw, ig, p->res);
> dev_err(&cxlr->dev,
> - "%s:%s %s got iw: %d ig: %d state: %s %#llx:%#llx\n",
> + "%s:%s %s got iw: %d ig: %d state: %s %#llx-%#llx:%#llx-%#llx(%s):%#llx-%#llx(%s)\n",
> dev_name(port->uport_dev), dev_name(&port->dev),
> __func__, cxld->interleave_ways,
> cxld->interleave_granularity,
> (cxld->flags & CXL_DECODER_F_ENABLE) ?
> "enabled" :
> "disabled",
> - cxld->hpa_range.start, cxld->hpa_range.end);
> + p->res->start, p->res->end,
> + cxled->spa_range.start, cxled->spa_range.end,
> + dev_name(&cxled->cxld.dev),
> + cxld->hpa_range.start, cxld->hpa_range.end,
> + dev_name(&cxld->dev));
> return -ENXIO;
> }
> } else {
> --
> 2.39.5
>
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