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Message-ID: <Z7Z-lcV7BAn1M0Gt@gourry-fedora-PF4VCD3F>
Date: Wed, 19 Feb 2025 20:00:05 -0500
From: Gregory Price <gourry@...rry.net>
To: Robert Richter <rrichter@....com>
Cc: Alison Schofield <alison.schofield@...el.com>,
Vishal Verma <vishal.l.verma@...el.com>,
Ira Weiny <ira.weiny@...el.com>,
Dan Williams <dan.j.williams@...el.com>,
Jonathan Cameron <Jonathan.Cameron@...wei.com>,
Dave Jiang <dave.jiang@...el.com>,
Davidlohr Bueso <dave@...olabs.net>, linux-cxl@...r.kernel.org,
linux-kernel@...r.kernel.org,
"Fabio M. De Francesco" <fabio.m.de.francesco@...ux.intel.com>,
Terry Bowman <terry.bowman@....com>
Subject: Re: [PATCH v2 00/15] cxl: Address translation support, part 2:
Generic support and AMD Zen5 platform enablement
On Tue, Feb 18, 2025 at 02:23:41PM +0100, Robert Richter wrote:
> This patch set adds support of address translation and enables this
> for AMD Zen5 platforms. This is a new appoach in response to an
> earlier attempt to implement CXL address translation [1] and the
> comments on it, esp. Dan's [2]. Dan suggested to solve this by walking
> the port hierarchy from the host port to the host bridge. When
> crossing memory domains from one port to the other, HPA translations
> are applied using a callback function to handle platform specifics.
>
> This series bases on:
>
> [PATCH v3 00/18] cxl: Address translation support, part 1: Cleanups and refactoring
>
> Purpose of patches:
> * Patches #1-#2: Introduction of address translation callback,
> * Patches #3-#12: Functional changes for address
> translation (common code).
> * #13: Architectural platform setup
> * Patch #15, #15: AMD Zen5 address translation.
>
> [1] https://lore.kernel.org/linux-cxl/20240701174754.967954-1-rrichter@amd.com/
> [2] https://lore.kernel.org/linux-cxl/669086821f136_5fffa29473@dwillia2-xfh.jf.intel.com.notmuch/
>
With the one build fix i've reported, I have tested this with Part 1 on
a Zen5 system w/ the PRM functionality.
Will review patches individually, but for the set:
Tested-by: Gregory Price <gourry@...rry.net>
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