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Message-ID: <c4f5c1fb-123d-4dd1-9885-031808f37419@quicinc.com>
Date: Thu, 20 Feb 2025 12:38:59 +0530
From: Jagadeesh Kona <quic_jkona@...cinc.com>
To: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
CC: Bjorn Andersson <andersson@...nel.org>,
Michael Turquette
<mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Rob Herring
<robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley
<conor+dt@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>,
Ajit Pandey
<quic_ajipan@...cinc.com>,
Imran Shaik <quic_imrashai@...cinc.com>,
"Taniya
Das" <quic_tdas@...cinc.com>,
Satya Priya Kakitapalli
<quic_skakitap@...cinc.com>,
<linux-arm-msm@...r.kernel.org>, <linux-clk@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 5/5] arm64: dts: qcom: Add MXC power domain to videocc
nodes
On 2/18/2025 11:02 PM, Dmitry Baryshkov wrote:
> On Tue, Feb 18, 2025 at 07:56:50PM +0530, Jagadeesh Kona wrote:
>> Videocc requires both MMCX and MXC rails to be powered ON
>> to configure the video PLLs on SM8450, SM8550 and SM8650
>> platforms. Hence add MXC power domain to videocc node on
>> these platforms.
>>
>> Signed-off-by: Jagadeesh Kona <quic_jkona@...cinc.com>
>> ---
>> arch/arm64/boot/dts/qcom/sm8450.dtsi | 3 ++-
>> arch/arm64/boot/dts/qcom/sm8550.dtsi | 3 ++-
>> arch/arm64/boot/dts/qcom/sm8650.dtsi | 3 ++-
>> 3 files changed, 6 insertions(+), 3 deletions(-)
>
> Three separate patches, please. With that in mind:
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@...aro.org>
>
Sure, will split this into separate patches.
Thanks,
Jagadeesh
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> index 9c809fc5fa45a98ff5441a0b6809931588897243..4f8dca8fc64212191780067c5d8815e3a2bb137f 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> @@ -3136,7 +3136,8 @@ videocc: clock-controller@...0000 {
>> reg = <0 0x0aaf0000 0 0x10000>;
>> clocks = <&rpmhcc RPMH_CXO_CLK>,
>> <&gcc GCC_VIDEO_AHB_CLK>;
>> - power-domains = <&rpmhpd RPMHPD_MMCX>;
>> + power-domains = <&rpmhpd RPMHPD_MMCX>,
>> + <&rpmhpd RPMHPD_MXC>;
>> required-opps = <&rpmhpd_opp_low_svs>;
>> #clock-cells = <1>;
>> #reset-cells = <1>;
>> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
>> index eac8de4005d82f246bc50f64f09515631d895c99..a039ae71e1b7bba8124128d19de5e00c65217770 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
>> @@ -2889,7 +2889,8 @@ videocc: clock-controller@...0000 {
>> reg = <0 0x0aaf0000 0 0x10000>;
>> clocks = <&bi_tcxo_div2>,
>> <&gcc GCC_VIDEO_AHB_CLK>;
>> - power-domains = <&rpmhpd RPMHPD_MMCX>;
>> + power-domains = <&rpmhpd RPMHPD_MMCX>,
>> + <&rpmhpd RPMHPD_MXC>;
>> required-opps = <&rpmhpd_opp_low_svs>;
>> #clock-cells = <1>;
>> #reset-cells = <1>;
>> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi
>> index 86684cb9a9325618ddb74458621cf4bbdc1cc0d1..32af2a0f7a0030f155b7d8c93faeffa384a42768 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi
>> @@ -3524,7 +3524,8 @@ videocc: clock-controller@...0000 {
>> reg = <0 0x0aaf0000 0 0x10000>;
>> clocks = <&bi_tcxo_div2>,
>> <&gcc GCC_VIDEO_AHB_CLK>;
>> - power-domains = <&rpmhpd RPMHPD_MMCX>;
>> + power-domains = <&rpmhpd RPMHPD_MMCX>,
>> + <&rpmhpd RPMHPD_MXC>;
>> #clock-cells = <1>;
>> #reset-cells = <1>;
>> #power-domain-cells = <1>;
>>
>> --
>> 2.34.1
>>
>
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