Message-ID:
 <BL3PR12MB6571FE73FA8D5AAB9FB4BB3CC9C42@BL3PR12MB6571.namprd12.prod.outlook.com>
Date: Thu, 20 Feb 2025 11:30:52 +0000
From: "Gupta, Suraj" <Suraj.Gupta2@....com>
To: Russell King <linux@...linux.org.uk>, Sean Anderson
	<sean.anderson@...ux.dev>
CC: Andrew Lunn <andrew@...n.ch>, "andrew+netdev@...n.ch"
	<andrew+netdev@...n.ch>, "davem@...emloft.net" <davem@...emloft.net>,
	"edumazet@...gle.com" <edumazet@...gle.com>, "kuba@...nel.org"
	<kuba@...nel.org>, "pabeni@...hat.com" <pabeni@...hat.com>, "Simek, Michal"
	<michal.simek@....com>, "Pandey, Radhey Shyam" <radhey.shyam.pandey@....com>,
	"horms@...nel.org" <horms@...nel.org>, "netdev@...r.kernel.org"
	<netdev@...r.kernel.org>, "linux-arm-kernel@...ts.infradead.org"
	<linux-arm-kernel@...ts.infradead.org>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>, "git (AMD-Xilinx)" <git@....com>, "Katakam,
 Harini" <harini.katakam@....com>
Subject: RE: [PATCH net-next 2/2] net: axienet: Add support for AXI 2.5G MAC

[AMD Official Use Only - AMD Internal Distribution Only]

> -----Original Message-----
> From: Russell King <linux@...linux.org.uk>
> Sent: Tuesday, November 19, 2024 9:19 PM
> To: Sean Anderson <sean.anderson@...ux.dev>
> Cc: Andrew Lunn <andrew@...n.ch>; Gupta, Suraj <Suraj.Gupta2@....com>;
> andrew+netdev@...n.ch; davem@...emloft.net; edumazet@...gle.com;
> kuba@...nel.org; pabeni@...hat.com; Simek, Michal <michal.simek@....com>;
> Pandey, Radhey Shyam <radhey.shyam.pandey@....com>; horms@...nel.org;
> netdev@...r.kernel.org; linux-arm-kernel@...ts.infradead.org; linux-
> kernel@...r.kernel.org; git (AMD-Xilinx) <git@....com>; Katakam, Harini
> <harini.katakam@....com>
> Subject: Re: [PATCH net-next 2/2] net: axienet: Add support for AXI 2.5G MAC
>
> Caution: This message originated from an External Source. Use proper caution
> when opening attachments, clicking links, or responding.
>
>
> On Tue, Nov 19, 2024 at 10:26:52AM -0500, Sean Anderson wrote:
> > On 11/18/24 20:35, Andrew Lunn wrote:
> > > On Mon, Nov 18, 2024 at 11:00:22AM -0500, Sean Anderson wrote:
> > >> On 11/18/24 10:56, Russell King (Oracle) wrote:
> > >> > On Mon, Nov 18, 2024 at 01:48:22PM +0530, Suraj Gupta wrote:
> > >> >> Add AXI 2.5G MAC support, which is an incremental speed upgrade
> > >> >> of AXI 1G MAC and supports 2.5G speed only. "max-speed" DT
> > >> >> property is used in driver to distinguish 1G and 2.5G MACs of AXI 1G/2.5G
> IP.
> > >> >> If max-speed property is missing, 1G is assumed to support
> > >> >> backward compatibility.
> > >> >>
> > >> >> Co-developed-by: Harini Katakam <harini.katakam@....com>
> > >> >> Signed-off-by: Harini Katakam <harini.katakam@....com>
> > >> >> Signed-off-by: Suraj Gupta <suraj.gupta2@....com>
> > >> >> ---
> > >> >
> > >> > ...
> > >> >
> > >> >> -       lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE |
> MAC_ASYM_PAUSE |
> > >> >> -               MAC_10FD | MAC_100FD | MAC_1000FD;
> > >> >> +       lp->phylink_config.mac_capabilities = MAC_SYM_PAUSE |
> > >> >> + MAC_ASYM_PAUSE;
> > >> >> +
> > >> >> +       /* Set MAC capabilities based on MAC type */
> > >> >> +       if (lp->max_speed == SPEED_1000)
> > >> >> +               lp->phylink_config.mac_capabilities |= MAC_10FD |
> MAC_100FD | MAC_1000FD;
> > >> >> +       else
> > >> >> +               lp->phylink_config.mac_capabilities |=
> > >> >> + MAC_2500FD;
> > >> >
> > >> > The MAC can only operate at (10M, 100M, 1G) _or_ 2.5G ?
> > >>
> > >> It's a PCS limitation. It either does (1000Base-X and/or SGMII) OR
> > >> (2500Base-X). The MAC itself doesn't have this limitation AFAIK.
> > >
> > >
> > > And can the PCS change between these modes? It is pretty typical to
> > > use SGMII for 10/100/1G and then swap to 2500BaseX for 2.5G.
> >
> > Not AFAIK. There's only a bit for switching between 1000Base-X and
> > SGMII. 2500Base-X is selected at synthesis time, and AIUI the serdes
> > settings are different.
>
> Okay. First it was a PCS limitation. Then it was a MAC limitation. Now it's a
> synthesis limitation.
>
> I'm coming to the conclusion that those I'm communicating with don't actually know,
> and are just throwing random thoughts out there.
>
> Please do the research, and come back to me with a real and complete answer, not
> some hand-wavey "it's a limitation of X, no it's a limitation of Y, no it's a limitation of
> Z" which looks like no one really knows the correct answer.
>
> Just because the PCS doesn't have a bit that selects 2500base-X is meaningless.
> 2500base-X is generally implemented by upclocking 1000base-X by 2.5x. Marvell
> does this at their Serdes, there is no configuration at the MAC/PCS for 2.5G speeds.
>
> The same is true of 10GBASE-R vs 5GBASE-R in Marvell - 5GBASE-R is just the
> serdes clocking the MAC/PCS at half the rate that 10GBASE-R would run at.
>
> I suspect this Xilinx hardware is just the same - clock the transmit path it at
> 62.5MHz, and you get 1G speeds. Clock it at 156.25MHz, and you get 2.5G speeds.
>

Sorry for picking up this thread after long time, we checked internally with AMD IP and hardware experts and it is true that you can use this MAC and PCS to operate at 1G and 2.5G both. It is also possible to switch between these two speeds dynamically using external GT and/or if an external RTL logic is implemented in the FPGA. That will include some GPIO or register based selections to change the clock and configurations to switch between the speeds. Our current solution does not support this and is meant for a static speed selection only.
If some user wants to implement dynamic speed switching solution, that will need to be accompanied by additional software changes later.

We'll use MAC ability register to detect if MAC is configured for 2.5G. Will it be fine to advertise both 1G and 2.5G in that case?

> Thanks.
>
> --
> RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
> FTTP is here! 80Mbps down 10Mbps up. Decent connectivity at last!

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