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Message-Id: <20250221170452.875419-1-matthew.gerlach@linux.intel.com>
Date: Fri, 21 Feb 2025 11:04:50 -0600
From: Matthew Gerlach <matthew.gerlach@...ux.intel.com>
To: lpieralisi@...nel.org,
	kw@...ux.com,
	manivannan.sadhasivam@...aro.org,
	robh@...nel.org,
	bhelgaas@...gle.com,
	krzk+dt@...nel.org,
	conor+dt@...nel.org,
	joyce.ooi@...el.com,
	linux-pci@...r.kernel.org,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org
Cc: matthew.gerlach@...era.com,
	peter.colberg@...era.com,
	Matthew Gerlach <matthew.gerlach@...ux.intel.com>
Subject: [PATCH v8 0/2] Add PCIe Root Port support for Agilex family of chips

This patch set adds PCIe Root Port support for the Agilex family of FPGA chips.

Patch 1:
  Add new compatible strings for the three variants of the Agilex PCIe
  controller IP.

Patch 2:
  Update Altera PCIe controller driver to support the Agilex family of chips.

Previous versions of this patch set contained patches unrelated to PCIe 
Root Port support for Agilex chips. These patches have been removed and
will be resubmitted separately. Patches related to a particular FPGA
design have also been removed.

D M, Sharath Kumar (1):
  PCI: altera: Add Agilex support

Matthew Gerlach (1):
  dt-bindings: PCI: altera: Add binding for Agilex

 .../bindings/pci/altr,pcie-root-port.yaml     |  10 +
 drivers/pci/controller/pcie-altera.c          | 253 +++++++++++++++++-
 2 files changed, 254 insertions(+), 9 deletions(-)

-- 
2.34.1


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