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Message-ID: <174017123873.53026.16356740656319644564.robh@kernel.org>
Date: Fri, 21 Feb 2025 14:54:03 -0600
From: "Rob Herring (Arm)" <robh@...nel.org>
To: Jagadeesh Kona <quic_jkona@...cinc.com>
Cc: Imran Shaik <quic_imrashai@...cinc.com>,
Satya Priya Kakitapalli <quic_skakitap@...cinc.com>,
Konrad Dybcio <konradybcio@...nel.org>,
linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org,
Taniya Das <quic_tdas@...cinc.com>,
Michael Turquette <mturquette@...libre.com>,
linux-clk@...r.kernel.org, Stephen Boyd <sboyd@...nel.org>,
devicetree@...r.kernel.org, Bjorn Andersson <andersson@...nel.org>,
Ajit Pandey <quic_ajipan@...cinc.com>,
Conor Dooley <conor+dt@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>
Subject: Re: [PATCH 1/5] dt-bindings: clock: qcom,sm8450-videocc: Add MXC
power domain
On Tue, 18 Feb 2025 19:56:46 +0530, Jagadeesh Kona wrote:
> To configure the video PLLs and enable the video GDSCs on SM8450,
> SM8475, SM8550 and SM8650 platforms, the MXC rail must be ON along
> with MMCX. Therefore, update the videocc bindings to include
> the MXC power domain on these platforms.
>
> Fixes: 1e910b2ba0ed ("dt-bindings: clock: qcom: Add SM8450 video clock controller")
> Signed-off-by: Jagadeesh Kona <quic_jkona@...cinc.com>
> ---
> Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
Acked-by: Rob Herring (Arm) <robh@...nel.org>
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