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Message-ID: <174014502450.10177.11575730496333668201.tip-bot2@tip-bot2>
Date: Fri, 21 Feb 2025 13:37:04 -0000
From: "tip-bot2 for Brian Ochoa" <tip-bot2@...utronix.de>
To: linux-tip-commits@...r.kernel.org
Cc: Brian Ochoa <brianeochoa@...il.com>, Ingo Molnar <mingo@...nel.org>,
x86@...nel.org, linux-kernel@...r.kernel.org
Subject: [tip: x86/urgent] docs: arch/x86/sva: Fix two grammar errors under
Background and FAQ
The following commit has been merged into the x86/urgent branch of tip:
Commit-ID: c9876cdb3ac4dcdf3c710ff02094165982e2a557
Gitweb: https://git.kernel.org/tip/c9876cdb3ac4dcdf3c710ff02094165982e2a557
Author: Brian Ochoa <brianeochoa@...il.com>
AuthorDate: Wed, 19 Feb 2025 10:09:20 -05:00
Committer: Ingo Molnar <mingo@...nel.org>
CommitterDate: Fri, 21 Feb 2025 14:24:51 +01:00
docs: arch/x86/sva: Fix two grammar errors under Background and FAQ
- Correct "in order" to "in order to"
- Append missing quantifier
Signed-off-by: Brian Ochoa <brianeochoa@...il.com>
Signed-off-by: Ingo Molnar <mingo@...nel.org>
Link: https://lore.kernel.org/r/20250219150920.445802-1-brianeochoa@gmail.com
---
Documentation/arch/x86/sva.rst | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/arch/x86/sva.rst b/Documentation/arch/x86/sva.rst
index 33cb050..6a75998 100644
--- a/Documentation/arch/x86/sva.rst
+++ b/Documentation/arch/x86/sva.rst
@@ -25,7 +25,7 @@ to cache translations for virtual addresses. The IOMMU driver uses the
mmu_notifier() support to keep the device TLB cache and the CPU cache in
sync. When an ATS lookup fails for a virtual address, the device should
use the PRI in order to request the virtual address to be paged into the
-CPU page tables. The device must use ATS again in order the fetch the
+CPU page tables. The device must use ATS again in order to fetch the
translation before use.
Shared Hardware Workqueues
@@ -216,7 +216,7 @@ submitting work and processing completions.
Single Root I/O Virtualization (SR-IOV) focuses on providing independent
hardware interfaces for virtualizing hardware. Hence, it's required to be
-almost fully functional interface to software supporting the traditional
+an almost fully functional interface to software supporting the traditional
BARs, space for interrupts via MSI-X, its own register layout.
Virtual Functions (VFs) are assisted by the Physical Function (PF)
driver.
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