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Message-ID: <Z7nkvQ1dRFI+solj@dragon>
Date: Sat, 22 Feb 2025 22:52:45 +0800
From: Shawn Guo <shawnguo2@...h.net>
To: Antonin Godard <antonin.godard@...tlin.com>
Cc: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>,
Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
imx@...ts.linux.dev, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v2 3/3] ARM: dts: imx6ul: Add Variscite Concerto board
support
On Mon, Jan 27, 2025 at 04:31:02PM +0100, Antonin Godard wrote:
> Add support for the Variscite Concerto Carrier Board with:
>
> - LVDS interface for the VLCD-CAP-GLD-LVDS 7" LCD 800 x 480 touch
> display (not configured)
> - USB Host + USB OTG Connector
> - 10/100 Mbps Ethernet
> - miniPCI-Express slot
> - SD Card connector
> - Audio Headphone/Line In jack connectors
> - S-ATA
> - On-board DMIC
>
> Product Page: https://www.variscite.com/product/single-board-computers/concerto-board
>
> This file is based on the one provided by Variscite on their own kernel,
> but adapted for mainline.
>
> Signed-off-by: Antonin Godard <antonin.godard@...tlin.com>
> ---
> arch/arm/boot/dts/nxp/imx/Makefile | 1 +
> .../boot/dts/nxp/imx/imx6ul-var-som-concerto.dts | 320 +++++++++++++++++++++
> 2 files changed, 321 insertions(+)
>
> diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile
> index 39a153536d2a..94c9bc94cc8e 100644
> --- a/arch/arm/boot/dts/nxp/imx/Makefile
> +++ b/arch/arm/boot/dts/nxp/imx/Makefile
> @@ -329,6 +329,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
> imx6ul-tx6ul-0010.dtb \
> imx6ul-tx6ul-0011.dtb \
> imx6ul-tx6ul-mainboard.dtb \
> + imx6ul-var-som-concerto.dtb \
> imx6ull-14x14-evk.dtb \
> imx6ull-colibri-aster.dtb \
> imx6ull-colibri-emmc-aster.dtb \
> diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
> new file mode 100644
> index 000000000000..4955d5193be3
> --- /dev/null
> +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
> @@ -0,0 +1,320 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-MX6UL
> + * Variscite SoM mounted on it
> + *
> + * Copyright 2019 Variscite Ltd.
> + * Copyright 2025 Bootlin
> + */
> +
> +#include "imx6ul-var-som.dtsi"
> +#include <dt-bindings/leds/common.h>
> +
> +/ {
> + model = "Variscite VAR-SOM-MX6UL Concerto Board";
> + compatible = "variscite,mx6ulconcerto", "variscite,var-som-imx6ul", "fsl,imx6ul";
> +
> + chosen {
> + stdout-path = &uart1;
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_gpio_key_back>, <&pinctrl_gpio_key_wakeup>;
> +
> + key-back {
> + gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
> + linux,code = <KEY_BACK>;
> + };
> +
> + key-wakeup {
> + gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
> + linux,code = <KEY_WAKEUP>;
> + wakeup-source;
> + };
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_gpio_leds>;
> +
> + led-0 {
> + function = LED_FUNCTION_STATUS;
> + color = <LED_COLOR_ID_GREEN>;
> + label = "gpled2";
> + gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "heartbeat";
> + };
> + };
> +};
> +
> +&can1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexcan1>;
> + status = "okay";
> +};
> +
> +&fec1 {
> + status = "disabled";
> +};
> +
> +&fec2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_gpio>, <&pinctrl_enet2_mdio>;
> + phy-mode = "rmii";
> + phy-handle = <ðphy1>;
> + phy-reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
> + phy-reset-duration = <100>;
Deprecated properties. They should be described by ethernet-phy.
> + status = "okay";
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethphy1: ethernet-phy@3 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + micrel,rmii-reference-clock-select-25-mhz = <1>;
> + micrel,led-mode = <0>;
> + clocks = <&rmii_ref_clk>;
> + clock-names = "rmii-ref";
> + reg = <3>;
> + };
> + };
> +};
> +
> +&i2c1 {
> + clock-frequency = <100000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c1>;
> + status = "okay";
> +
> + rtc@68 {
> + /*
> + * To actually use this interrupt
> + * connect pins J14.8 & J14.10 on the Concerto-Board.
> + */
> + compatible = "dallas,ds1337";
> + reg = <0x68>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_rtc>;
> + interrupt-parent = <&gpio1>;
> + interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
> + };
> +};
> +
> +&iomuxc {
> + pinctrl_enet2: enet2grp {
> + fsl,pins = <
> + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
> + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
> + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
> + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
> + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
> + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
> + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
> + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
> + >;
> + };
> +
> + pinctrl_enet2_mdio: enet2-mdiogrp {
> + fsl,pins = <
> + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
> + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
> + >;
> + };
> +
> + pinctrl_enet2_gpio: enet2-gpiogrp {
> + fsl,pins = <
> + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* fec2 reset */
> + >;
> + };
> +
> + pinctrl_flexcan1: flexcan1grp {
> + fsl,pins = <
> + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
> + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
> + >;
> + };
> +
> + pinctrl_gpio_key_back: gpio-key-backgrp {
> + fsl,pins = <
> + MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x17059 /* Back */
> + >;
> + };
> +
> + pinctrl_gpio_leds: gpio-ledsgrp {
> + fsl,pins = <
> + MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x1b0b0 /* GPLED2 */
> + >;
> + };
> +
> + pinctrl_i2c1: i2c1grp {
> + fsl,pins = <
> + MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
> + MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0
> + >;
> + };
> +
> + pinctrl_pwm4: pwm4grp {
> + fsl,pins = <
> + MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x110b0
> + >;
> + };
> +
> + pinctrl_rtc: rtcgrp {
> + fsl,pins = <
> + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x1b0b0 /* RTC alarm IRQ */
> + >;
> + };
> +
> + pinctrl_uart1: uart1grp {
> + fsl,pins = <
> + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
> + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
> + >;
> + };
> +
> + pinctrl_uart5: uart5grp {
> + fsl,pins = <
> + MX6UL_PAD_CSI_DATA00__UART5_DCE_TX 0x1b0b1
> + MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x1b0b1
> + MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1
> + MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1
> + >;
> + };
> +
> + pinctrl_usb_otg1_id: usbotg1idgrp {
> + fsl,pins = <
> + MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID 0x17059
> + >;
> + };
> +
> + pinctrl_wdog: wdoggrp {
> + fsl,pins = <
> + MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B 0x78b0
> + >;
> + };
> +
> + pinctrl_gpio_key_wakeup: gpio-keys-wakeupgrp {
Out of alphabetic order.
> + fsl,pins = <
> + MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x17059 /* Wakeup */
> + >;
> + };
> +
> + pinctrl_usdhc1: usdhc1grp {
> + fsl,pins = <
> + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
> + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059
> + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
> + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
> + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
> + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
> + >;
> + };
> +
> + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
> + fsl,pins = <
> + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
> + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
> + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
> + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
> + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
> + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
> + >;
> + };
> +
> + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
> + fsl,pins = <
> + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
> + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
> + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
> + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
> + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
> + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
> + >;
> + };
> +
> + pinctrl_usdhc1_gpio: usdhc1-gpiogrp {
> + fsl,pins = <
> + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x1b0b1 /* CD */
> + >;
> + };
> +};
> +
> +&pwm4 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm4>;
> + status = "okay";
> +};
> +
> +&snvs_pwrkey {
> + status = "disabled";
> +};
> +
> +&snvs_rtc {
> + status = "disabled";
> +};
> +
> +&tsc {
> + /*
> + * Conflics with wdog1 ext-reset-output & SD CD pins,
> + * so we keep it disabled by default.
> + */
> + status = "disabled";
> +};
> +
> +/* Console UART */
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart1>;
> + status = "okay";
> +};
> +
> +/* ttymxc4 UART */
> +&uart5 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart5>;
> + uart-has-rtscts;
> + status = "okay";
> +};
> +
> +&usbotg1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usb_otg1_id>;
> + dr_mode = "otg";
> + disable-over-current;
> + srp-disable;
> + hnp-disable;
> + adp-disable;
> + status = "okay";
> +};
> +
> +&usbotg2 {
> + dr_mode = "host";
> + disable-over-current;
> + status = "okay";
> +};
> +
> +&wdog1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_wdog>;
> + /*
> + * To actually use ext-reset-output
> + * connect pins J17.3 & J17.8 on the Concerto-Board
> + */
> + fsl,ext-reset-output;
> +};
> +
> +&usdhc1 {
Out of alphabetic order.
Shawn
> + pinctrl-names = "default", "state_100mhz", "state_200mhz";
> + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
> + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
> + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
> + cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
> + no-1-8-v;
> + keep-power-in-suspend;
> + wakeup-source;
> + status = "okay";
> +};
>
> --
> 2.47.0.2.g7caf9f4c55.dirty
>
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