linux-kernel - RE: [PATCH v4 2/2] PCI: xilinx-cpm: Add support for Versal Net CPM5NC Root Port controller

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID:
 <SN7PR12MB7201DD2E33A18770C04DCDDC8BC02@SN7PR12MB7201.namprd12.prod.outlook.com>
Date: Mon, 24 Feb 2025 15:51:14 +0000
From: "Havalige, Thippeswamy" <thippeswamy.havalige@....com>
To: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
CC: "bhelgaas@...gle.com" <bhelgaas@...gle.com>, "lpieralisi@...nel.org"
	<lpieralisi@...nel.org>, "kw@...ux.com" <kw@...ux.com>, "robh@...nel.org"
	<robh@...nel.org>, "krzk+dt@...nel.org" <krzk+dt@...nel.org>,
	"conor+dt@...nel.org" <conor+dt@...nel.org>, "linux-pci@...r.kernel.org"
	<linux-pci@...r.kernel.org>, "devicetree@...r.kernel.org"
	<devicetree@...r.kernel.org>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>, "Simek, Michal" <michal.simek@....com>,
	"Gogada, Bharat Kumar" <bharat.kumar.gogada@....com>
Subject: RE: [PATCH v4 2/2] PCI: xilinx-cpm: Add support for Versal Net CPM5NC
 Root Port controller

[AMD Official Use Only - AMD Internal Distribution Only]

Thanks for reviewing, I have updated and sent latest patch
With below review comment.

Regards,
Thippeswamy H

> -----Original Message-----
> From: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
> Sent: Monday, February 24, 2025 1:37 PM
> To: Havalige, Thippeswamy <thippeswamy.havalige@....com>
> Cc: bhelgaas@...gle.com; lpieralisi@...nel.org; kw@...ux.com;
> robh@...nel.org; krzk+dt@...nel.org; conor+dt@...nel.org; linux-
> pci@...r.kernel.org; devicetree@...r.kernel.org; linux-
> kernel@...r.kernel.org; Simek, Michal <michal.simek@....com>; Gogada,
> Bharat Kumar <bharat.kumar.gogada@....com>
> Subject: Re: [PATCH v4 2/2] PCI: xilinx-cpm: Add support for Versal Net
> CPM5NC Root Port controller
>
> On Mon, Feb 24, 2025 at 01:11:43PM +0530, Thippeswamy Havalige wrote:
> > The Versal Net ACAP (Adaptive Compute Acceleration Platform) devices
> > incorporate the Coherency and PCIe Gen5 Module, specifically the
> > Next-Generation Compact Module (CPM5NC).
> >
> > The integrated CPM5NC block, along with the built-in bridge, can
> > function as a PCIe Root Port & supports the PCIe Gen5 protocol with
> > data transfer rates of up to 32 GT/s, capable of supporting up to a
> > x16 lane-width configuration.
> >
> > Bridge errors are managed using a specific interrupt line designed for
> > CPM5N. INTx interrupt support is not available.
> >
> > Currently in this commit platform specific Bridge errors support is
> > not added.
> >
> > Signed-off-by: Thippeswamy Havalige <thippeswamy.havalige@....com>
>
> Reviewed-by: Manivannan Sadhasivam
> <manivannan.sadhasivam@...aro.org>
>
> One comment below which is not related to *this* patch, but should be fixed
> separately (ideally before this patch).
>
> > ---
> > Changes in v2:
> > - Update commit message.
> > Changes in v3:
> > - Address review comments.
> > ---
> >  drivers/pci/controller/pcie-xilinx-cpm.c | 40
> > +++++++++++++++++-------
> >  1 file changed, 29 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/pci/controller/pcie-xilinx-cpm.c
> > b/drivers/pci/controller/pcie-xilinx-cpm.c
> > index 81e8bfae53d0..a0815c5010d9 100644
> > --- a/drivers/pci/controller/pcie-xilinx-cpm.c
> > +++ b/drivers/pci/controller/pcie-xilinx-cpm.c
> > @@ -84,6 +84,7 @@ enum xilinx_cpm_version {
> >     CPM,
> >     CPM5,
> >     CPM5_HOST1,
> > +   CPM5NC_HOST,
> >  };
> >
> >  /**
> > @@ -478,6 +479,9 @@ static void xilinx_cpm_pcie_init_port(struct
> > xilinx_cpm_pcie *port)  {
> >     const struct xilinx_cpm_variant *variant = port->variant;
> >
> > +   if (variant->version != CPM5NC_HOST)
> > +           return;
> > +
> >     if (cpm_pcie_link_up(port))
> >             dev_info(port->dev, "PCIe Link is UP\n");
> >     else
> > @@ -578,16 +582,18 @@ static int xilinx_cpm_pcie_probe(struct
> > platform_device *pdev)
> >
> >     port->dev = dev;
> >
> > -   err = xilinx_cpm_pcie_init_irq_domain(port);
> > -   if (err)
> > -           return err;
> > +   port->variant = of_device_get_match_data(dev);
> > +
> > +   if (port->variant->version != CPM5NC_HOST) {
> > +           err = xilinx_cpm_pcie_init_irq_domain(port);
> > +           if (err)
> > +                   return err;
> > +   }
> >
> >     bus = resource_list_first_type(&bridge->windows, IORESOURCE_BUS);
> >     if (!bus)
> >             return -ENODEV;
>
> Here, xilinx_cpm_free_irq_domains() should be called in the error path.
>
> - Mani
>
> --
> மணிவண்ணன் சதாசிவம்