linux-kernel - Re: [PATCH 5/5] arm64: dts: mba8xx: Add PCIe support

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Message-ID: <Z7zCyHtpKo0WAPMh@lizhi-Precision-Tower-5810>
Date: Mon, 24 Feb 2025 14:04:40 -0500
From: Frank Li <Frank.li@....com>
To: Alexander Stein <alexander.stein@...tq-group.com>
Cc: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>, Shawn Guo <shawnguo@...nel.org>,
	Sascha Hauer <s.hauer@...gutronix.de>,
	Pengutronix Kernel Team <kernel@...gutronix.de>,
	Fabio Estevam <festevam@...il.com>, devicetree@...r.kernel.org,
	imx@...ts.linux.dev, linux-arm-kernel@...ts.infradead.org,
	linux-kernel@...r.kernel.org, linux@...tq-group.com
Subject: Re: [PATCH 5/5] arm64: dts: mba8xx: Add PCIe support

On Tue, Jan 07, 2025 at 03:01:10PM +0100, Alexander Stein wrote:
> Add PCIe support for TQMa8Xx on MBa8Xx board.
>
> Signed-off-by: Alexander Stein <alexander.stein@...tq-group.com>
> ---
>  arch/arm64/boot/dts/freescale/mba8xx.dtsi | 32 +++++++++++++++++++----
>  1 file changed, 27 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/mba8xx.dtsi b/arch/arm64/boot/dts/freescale/mba8xx.dtsi
> index 276d1683b03bb..117f657283191 100644
> --- a/arch/arm64/boot/dts/freescale/mba8xx.dtsi
> +++ b/arch/arm64/boot/dts/freescale/mba8xx.dtsi
> @@ -36,6 +36,13 @@ chosen {
>  		stdout-path = &lpuart1;
>  	};
>
> +	/* Non-controllable PCIe reference clock generator */
> +	pcie_refclk: clock-pcie-ref {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <100000000>;
> +	};
> +
>  	gpio-keys {
>  		compatible = "gpio-keys";
>  		pinctrl-names = "default";
> @@ -208,6 +215,12 @@ &flexcan2 {
>  	status = "okay";
>  };
>
> +&hsio_phy {
> +	fsl,hsio-cfg = "pciea-x2-pcieb";
> +	fsl,refclk-pad-mode = "input";
> +	status = "okay";
> +};
> +
>  &i2c1 {
>  	tlv320aic3x04: audio-codec@18 {
>  		compatible = "ti,tlv320aic32x4";
> @@ -309,7 +322,16 @@ &lsio_gpio3 {
>  			  "", "", "", "";
>  };
>
> -/* TODO: Mini-PCIe */
> +&pcieb {
> +	phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>;
> +	phy-names = "pcie-phy";
> +	pinctrl-0 = <&pinctrl_pcieb>;
> +	pinctrl-names = "default";
> +	reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
> +	disable-gpio = <&expander 7 GPIO_ACTIVE_LOW>;

"disable-gpio" is undocument property.

Frank Li

> +	vpcie-supply = <&reg_pcie_1v5>;
> +	status = "okay";
> +};
>
>  &sai1 {
>  	assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
> @@ -467,10 +489,10 @@ pinctrl_pca9538: pca9538grp {
>  		fsl,pins = <IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19	0x00000020>;
>  	};
>
> -	pinctrl_pcieb: pcieagrp {
> -		fsl,pins = <IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00	0x06000041>,
> -			   <IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01	0x06000041>,
> -			   <IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02	0x04000041>;
> +	pinctrl_pcieb: pciebgrp {
> +		fsl,pins = <IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00		0x06000041>,
> +			   <IMX8QXP_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B	0x06000041>,
> +			   <IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02		0x04000041>;
>  	};
>
>  	pinctrl_reg_pcie_1v5: regpcie1v5grp {
> --
> 2.34.1
>