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Message-ID: <20250224200347.GA4011821-robh@kernel.org>
Date: Mon, 24 Feb 2025 14:03:47 -0600
From: Rob Herring <robh@...nel.org>
To: Andy Yan <andyshrk@....com>
Cc: heiko@...ech.de, hjc@...k-chips.com, mripard@...nel.org,
cristian.ciocaltea@...labora.com, neil.armstrong@...aro.org,
yubing.zhang@...k-chips.com, krzk+dt@...nel.org,
devicetree@...r.kernel.org, dri-devel@...ts.freedesktop.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-rockchip@...ts.infradead.org, sebastian.reichel@...labora.com,
Andy Yan <andy.yan@...k-chips.com>
Subject: Re: [PATCH 1/6] dt-bindings: display: rockchip: Add schema for
RK3588 DPTX Controller
On Sun, Feb 23, 2025 at 07:30:24PM +0800, Andy Yan wrote:
> From: Andy Yan <andy.yan@...k-chips.com>
>
> The Rockchip RK3588 SoC integrates the Synopsys DesignWare DPTX
> controller. And this DPTX controller need share a USBDP PHY with
> the USB 3.0 OTG controller during operation.
>
> Signed-off-by: Andy Yan <andy.yan@...k-chips.com>
>
> ---
>
> .../display/rockchip/rockchip,dw-dp.yaml | 150 ++++++++++++++++++
> 1 file changed, 150 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip,dw-dp.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-dp.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-dp.yaml
> new file mode 100644
> index 000000000000..b48af8c3e68b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-dp.yaml
> @@ -0,0 +1,150 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-dp.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Rockchip DW DisplayPort Transmitter
> +
> +maintainers:
> + - Andy Yan <andy.yan@...k-chips.com>
> +
> +description: |
> + The Rockchip RK3588 SoC integrates the Synopsys DesignWare DPTX controller
> + which is compliant with the DisplayPort Specification Version 1.4 with the
> + following features:
> +
> + * DisplayPort 1.4a
> + * Main Link: 1/2/4 lanes
> + * Main Link Support 1.62Gbps, 2.7Gbps, 5.4Gbps and 8.1Gbps
> + * AUX channel 1Mbps
> + * Single Stream Transport(SST)
> + * Multistream Transport (MST)
> + *Type-C support (alternate mode)
??? ^
Otherwise,
Reviewed-by: Rob Herring (Arm) <robh@...nel.org>
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