linux-kernel - Re: [PATCH v8 1/2] dt-bindings: PCI: altera: Add binding for Agilex

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <20250224063326.kbuknwwhx5kyhgad@thinkpad>
Date: Mon, 24 Feb 2025 12:03:26 +0530
From: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
To: Matthew Gerlach <matthew.gerlach@...ux.intel.com>
Cc: lpieralisi@...nel.org, kw@...ux.com, robh@...nel.org,
	bhelgaas@...gle.com, krzk+dt@...nel.org, conor+dt@...nel.org,
	joyce.ooi@...el.com, linux-pci@...r.kernel.org,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
	matthew.gerlach@...era.com, peter.colberg@...era.com
Subject: Re: [PATCH v8 1/2] dt-bindings: PCI: altera: Add binding for Agilex

On Fri, Feb 21, 2025 at 11:04:51AM -0600, Matthew Gerlach wrote:
> Add the compatible bindings for the three variants of Agilex
> PCIe Hard IP.
> 
> Signed-off-by: Matthew Gerlach <matthew.gerlach@...ux.intel.com>

Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>

- Mani

> Reviewed-by: Rob Herring (Arm) <robh@...nel.org>
> ---
> v8:
>  - Removed patches unrelated to Agilex PCIe root port support from set.
>  - Removed patches related to a specific FPGA configuration from set.
> ---
>  .../devicetree/bindings/pci/altr,pcie-root-port.yaml   | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
> index 52533fccc134..1f93120d8eef 100644
> --- a/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
> +++ b/Documentation/devicetree/bindings/pci/altr,pcie-root-port.yaml
> @@ -12,9 +12,19 @@ maintainers:
>  
>  properties:
>    compatible:
> +    description: Each family of socfpga has its own implementation
> +      of the pci controller. altr,pcie-root-port-1.0 is used for the Cyclone5
> +      family of chips. The Stratix10 family of chips is supported
> +      by altr,pcie-root-port-2.0. The Agilex family of chips has
> +      three, non-register compatible, variants of PCIe Hard IP referred to as
> +      the f-tile, p-tile, and r-tile, depending on the specific chip instance.
> +
>      enum:
>        - altr,pcie-root-port-1.0
>        - altr,pcie-root-port-2.0
> +      - altr,pcie-root-port-3.0-f-tile
> +      - altr,pcie-root-port-3.0-p-tile
> +      - altr,pcie-root-port-3.0-r-tile
>  
>    reg:
>      items:
> -- 
> 2.34.1
> 

-- 
மணிவண்ணன் சதாசிவம்