linux-kernel - Re: [PATCH net-next 2/2] net: mdio: mdio-i2c: Add support for single-byte SMBus operations

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Message-ID: <20250224110315.62fb8c80@fedora>
Date: Mon, 24 Feb 2025 11:03:15 +0100
From: Maxime Chevallier <maxime.chevallier@...tlin.com>
To: Andrew Lunn <andrew@...n.ch>
Cc: davem@...emloft.net, Jakub Kicinski <kuba@...nel.org>, Eric Dumazet
 <edumazet@...gle.com>, Paolo Abeni <pabeni@...hat.com>, Russell King
 <linux@...linux.org.uk>, Heiner Kallweit <hkallweit1@...il.com>,
 netdev@...r.kernel.org, linux-kernel@...r.kernel.org,
 thomas.petazzoni@...tlin.com, Florian Fainelli <f.fainelli@...il.com>,
 Köry Maincent <kory.maincent@...tlin.com>, Simon Horman
 <horms@...nel.org>, Romain Gantois <romain.gantois@...tlin.com>, Antoine
 Tenart <atenart@...nel.org>, Marek Behún <kabel@...nel.org>
Subject: Re: [PATCH net-next 2/2] net: mdio: mdio-i2c: Add support for
 single-byte SMBus operations

On Mon, 24 Feb 2025 04:36:49 +0100
Andrew Lunn <andrew@...n.ch> wrote:

> > This was only tested on Copper SFP modules that embed a Marvell 88e1111
> > PHY.  
> 
> Does the Marvell PHY datasheet say what happens when you perform 8 bit
> accesses to 16 bit registers, such at the BMSR?

It doesn't specifically say what happens to BMSR, however the section
about "how to perform a random read" gives an example of a random
register read that is made of 2 single-byte reads, including the STOP
bit being set in-between reading the upper byte and the lower byte.

While this doesn't exactly specify the BMSR's latching behaviour, it
looks to me that this is a coherent way of reading a register state,
and BMSR's link status register *should* latch until the lower byte is
read.

I'll try it out with one of my modules to make sure though.

Maxime