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Message-ID: <CAGXv+5EBiYwjNeocGh0ZjWi5mzOZr_CfS6H+7au5vgQgeigUfg@mail.gmail.com>
Date: Mon, 24 Feb 2025 18:50:41 +0800
From: Chen-Yu Tsai <wenst@...omium.org>
To: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
Cc: linux-mediatek@...ts.infradead.org, robh@...nel.org, krzk+dt@...nel.org,
conor+dt@...nel.org, matthias.bgg@...il.com, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
kernel@...labora.com, pablo.sun@...iatek.com
Subject: Re: [PATCH v1 1/4] arm64: dts: mediatek: mt8188: Add base display
controller graph
On Thu, Feb 20, 2025 at 7:13 PM AngeloGioacchino Del Regno
<angelogioacchino.delregno@...labora.com> wrote:
>
> The display related IPs in MT8188 are flexible and support being
> interconnected with different instances of DDP IPs and/or with
> different DDP IPs, forming a full Display Data Path that ends
> with an actual display output, which is board specific.
>
> Add a common graph in the main mt8188.dtsi devicetree, which is
> shared between all of the currently supported boards.
> All boards featuring any display functionality will extend this
> common graph to hook the display controller of the SoC to their
> specific output port(s).
>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
Tested-by: Chen-Yu Tsai <wenst@...omium.org> # On MT8188 Ciri (int. and ext.)
> ---
> arch/arm64/boot/dts/mediatek/mt8188.dtsi | 140 +++++++++++++++++++++++
> 1 file changed, 140 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> index c226998b7e47..4437b1820f26 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi
> @@ -2868,6 +2868,23 @@ ovl0: ovl@...00000 {
> iommus = <&vdo_iommu M4U_PORT_L0_DISP_OVL0_RDMA0>;
> power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
> mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + ovl0_in: endpoint { };
> + };
> +
> + port@1 {
> + reg = <1>;
> + ovl0_out: endpoint {
> + remote-endpoint = <&rdma0_in>;
> + };
> + };
> + };
> };
>
> rdma0: rdma@...02000 {
> @@ -2878,6 +2895,25 @@ rdma0: rdma@...02000 {
> iommus = <&vdo_iommu M4U_PORT_L1_DISP_RDMA0>;
> power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
> mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + rdma0_in: endpoint {
> + remote-endpoint = <&ovl0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + rdma0_out: endpoint {
> + remote-endpoint = <&color0_in>;
> + };
> + };
> + };
> };
>
> color0: color@...03000 {
> @@ -2887,6 +2923,25 @@ color0: color@...03000 {
> interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
> mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + color0_in: endpoint {
> + remote-endpoint = <&rdma0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + color0_out: endpoint {
> + remote-endpoint = <&ccorr0_in>;
> + };
> + };
> + };
> };
>
> ccorr0: ccorr@...04000 {
> @@ -2896,6 +2951,25 @@ ccorr0: ccorr@...04000 {
> interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
> mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + ccorr0_in: endpoint {
> + remote-endpoint = <&color0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + ccorr0_out: endpoint {
> + remote-endpoint = <&aal0_in>;
> + };
> + };
> + };
> };
>
> aal0: aal@...05000 {
> @@ -2905,6 +2979,25 @@ aal0: aal@...05000 {
> interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
> mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + aal0_in: endpoint {
> + remote-endpoint = <&ccorr0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + aal0_out: endpoint {
> + remote-endpoint = <&gamma0_in>;
> + };
> + };
> + };
> };
>
> gamma0: gamma@...06000 {
> @@ -2914,6 +3007,23 @@ gamma0: gamma@...06000 {
> interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
> mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + gamma0_in: endpoint {
> + remote-endpoint = <&aal0_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + gamma0_out: endpoint { };
> + };
> + };
> };
>
> dither0: dither@...07000 {
> @@ -2923,6 +3033,21 @@ dither0: dither@...07000 {
> interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
> mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dither0_in: endpoint { };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dither0_out: endpoint { };
> + };
> + };
> };
>
> disp_dsi0: dsi@...08000 {
> @@ -3005,6 +3130,21 @@ postmask0: postmask@...1a000 {
> interrupts = <GIC_SPI 661 IRQ_TYPE_LEVEL_HIGH 0>;
> power-domains = <&spm MT8188_POWER_DOMAIN_VDOSYS0>;
> mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + postmask0_in: endpoint { };
> + };
> +
> + port@1 {
> + reg = <1>;
> + postmask0_out: endpoint { };
> + };
> + };
> };
>
> vdosys0: syscon@...1d000 {
> --
> 2.48.1
>
>
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