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Message-ID: <20250225115450.GO11590@noisy.programming.kicks-ass.net>
Date: Tue, 25 Feb 2025 12:54:50 +0100
From: Peter Zijlstra <peterz@...radead.org>
To: Dapeng Mi <dapeng1.mi@...ux.intel.com>
Cc: Ingo Molnar <mingo@...hat.com>,
Arnaldo Carvalho de Melo <acme@...nel.org>,
Namhyung Kim <namhyung@...nel.org>, Ian Rogers <irogers@...gle.com>,
Adrian Hunter <adrian.hunter@...el.com>,
Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
Kan Liang <kan.liang@...ux.intel.com>,
Andi Kleen <ak@...ux.intel.com>,
Eranian Stephane <eranian@...gle.com>, linux-kernel@...r.kernel.org,
linux-perf-users@...r.kernel.org, Dapeng Mi <dapeng1.mi@...el.com>
Subject: Re: [Patch v2 15/24] perf/x86/intel: Add SSP register support for
arch-PEBS
On Tue, Feb 18, 2025 at 03:28:09PM +0000, Dapeng Mi wrote:
> @@ -651,6 +651,16 @@ int x86_pmu_hw_config(struct perf_event *event)
> return -EINVAL;
> }
>
> + /* sample_regs_user never support SSP register. */
> + if (unlikely(event->attr.sample_regs_user & BIT_ULL(PERF_REG_X86_SSP)))
> + return -EINVAL;
We can easily enough read user SSP, no?
Should be possible even on todays machines; MSR_IA32_PL3_SSP provides.
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