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Message-ID: <20250226214751.3751865-1-robh@kernel.org>
Date: Wed, 26 Feb 2025 15:47:47 -0600
From: "Rob Herring (Arm)" <robh@...nel.org>
To: Andrew Lunn <andrew@...n.ch>,
Gregory Clement <gregory.clement@...tlin.com>,
Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>
Cc: linux-arm-kernel@...ts.infradead.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: [PATCH 1/3] arm64: dts: marvell: Move arch timer and pmu nodes to top-level
The Arm arch timer and PMU are not memory-mapped peripherals, and
therefore should not be under a "simple-bus" node. Move them to the
top-level like other platforms.
Signed-off-by: Rob Herring (Arm) <robh@...nel.org>
---
arch/arm64/boot/dts/marvell/armada-ap80x.dtsi | 29 ++++++++++---------
.../boot/dts/marvell/armada-ap810-ap0.dtsi | 18 ++++++------
2 files changed, 24 insertions(+), 23 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
index fdf88cd0eb02..e206d03a2867 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap80x.dtsi
@@ -48,6 +48,21 @@ tee@...0000 {
};
};
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a72-pmu";
+ interrupt-parent = <&pic>;
+ interrupts = <17>;
+ };
+
AP_NAME {
#address-cells = <2>;
#size-cells = <2>;
@@ -122,20 +137,6 @@ gic_v2m3: v2m@...000 {
};
};
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
- };
-
- pmu {
- compatible = "arm,cortex-a72-pmu";
- interrupt-parent = <&pic>;
- interrupts = <17>;
- };
-
odmi: odmi@...000 {
compatible = "marvell,odmi-controller";
msi-controller;
diff --git a/arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi b/arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi
index 2f9ab6b4a2c9..f5a89af154d4 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap810-ap0.dtsi
@@ -14,6 +14,7 @@ / {
compatible = "marvell,armada-ap810";
#address-cells = <2>;
#size-cells = <2>;
+ interrupt-parent = <&gic>;
aliases {
serial0 = &uart0_ap0;
@@ -25,11 +26,18 @@ psci {
method = "smc";
};
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+
ap810-ap0 {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
- interrupt-parent = <&gic>;
ranges;
config-space@...00000 {
@@ -62,14 +70,6 @@ gic_its_ap0: msi-controller@...0000 {
};
};
- timer {
- compatible = "arm,armv8-timer";
- interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
- <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
- };
-
xor@...000 {
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
reg = <0x400000 0x1000>,
--
2.47.2
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