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Message-ID: <e3713d6c-acf1-45eb-90a6-3a135a281562@kernel.org>
Date: Wed, 26 Feb 2025 10:42:40 +0100
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Jishnu Prakash <jishnu.prakash@....qualcomm.com>
Cc: jic23@...nel.org, robh@...nel.org, krzk+dt@...nel.org,
conor+dt@...nel.org, agross@...nel.org, andersson@...nel.org,
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Subject: Re: [PATCH V5 3/5] dt-bindings: iio: adc: Add support for QCOM PMIC5
Gen3 ADC
On 26/02/2025 09:51, Jishnu Prakash wrote:
>>> +
>>> + interrupts:
>>> + items:
>>> + - description: SDAM0 end of conversion (EOC) interrupt
>>> + - description: SDAM1 EOC interrupt
>>> + minItems: 1
>>
>> Same question.
>
> To explain why "reg" and "interrupts" are flexible:
>
> We need to add one item under each of these properties, per ADC SDAM. The number of PMIC SDAM peripherals allocated for ADC is not correlated with the PMIC used,
> it is programmed in FW (PBS) and is fixed per SOC, based on the SOC requirements.
>
> The number of ADC SDAMs used on a given SOC with a given PMIC (like PMK8550) will be fixed, but it is possible for
> the same PMIC to have 1 of its SDAMs allocated for ADC when used on one SOC and 2 SDAMs allocated for ADC when used on another SOC.
>
> All boards using a particular (SOC + PMIC) combination will have the same number of ADC SDAMs supported on that PMIC.
OK. Parts of above should be captured in commit msg or binding description.
Best regards,
Krzysztof
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