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Message-ID: <20250227123628.2931490-5-hchauhan@ventanamicro.com>
Date: Thu, 27 Feb 2025 18:06:22 +0530
From: Himanshu Chauhan <hchauhan@...tanamicro.com>
To: linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org,
linux-acpi@...r.kernel.org,
linux-efi@...r.kernel.org,
acpica-devel@...ts.linux.dev
Cc: paul.walmsley@...ive.com,
palmer@...belt.com,
lenb@...nel.org,
james.morse@....com,
tony.luck@...el.com,
ardb@...nel.org,
conor@...nel.org,
cleger@...osinc.com,
robert.moore@...el.com,
sunilvl@...tanamicro.com,
apatel@...tanamicro.com,
Himanshu Chauhan <hchauhan@...tanamicro.com>
Subject: [RFC PATCH v1 04/10] riscv: Add fixmap indices for GHES IRQ and SSE contexts
GHES error handling requires fixmap entries for IRQ notifications.
Add fixmap indices for IRQ, SSE Low and High priority notifications.
Signed-off-by: Himanshu Chauhan <hchauhan@...tanamicro.com>
---
arch/riscv/include/asm/fixmap.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/riscv/include/asm/fixmap.h b/arch/riscv/include/asm/fixmap.h
index 0a55099bb734..fa3a0ec0c55c 100644
--- a/arch/riscv/include/asm/fixmap.h
+++ b/arch/riscv/include/asm/fixmap.h
@@ -38,6 +38,14 @@ enum fixed_addresses {
FIX_TEXT_POKE0,
FIX_EARLYCON_MEM_BASE,
+#ifdef CONFIG_ACPI_APEI_GHES
+ /* Used for GHES mapping from assorted contexts */
+ FIX_APEI_GHES_IRQ,
+#ifdef CONFIG_RISCV_SSE
+ FIX_APEI_GHES_SSE_LOW_PRIORITY,
+ FIX_APEI_GHES_SSE_HIGH_PRIORITY,
+#endif /* CONFIG_RISCV_SSE */
+#endif /* CONFIG_ACPI_APEI_GHES */
__end_of_permanent_fixed_addresses,
/*
* Temporary boot-time mappings, used by early_ioremap(),
--
2.43.0
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