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Message-ID: <202502280006.8lJfdpzm-lkp@intel.com>
Date: Fri, 28 Feb 2025 00:32:29 +0800
From: kernel test robot <lkp@...el.com>
To: Thierry Bultel <thierry.bultel.yh@...renesas.com>,
thierry.bultel@...atsea.fr
Cc: oe-kbuild-all@...ts.linux.dev, linux-renesas-soc@...r.kernel.org,
geert@...ux-m68k.org, paul.barker.ct@...renesas.com,
Thierry Bultel <thierry.bultel.yh@...renesas.com>,
linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org
Subject: Re: [PATCH v3 06/13] clk: renesas: Add support for R9A09G077 SoC
Hi Thierry,
kernel test robot noticed the following build warnings:
[auto build test WARNING on tty/tty-testing]
[also build test WARNING on tty/tty-next tty/tty-linus geert-renesas-devel/next linus/master v6.14-rc4 next-20250227]
[cannot apply to geert-renesas-drivers/renesas-clk]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Thierry-Bultel/dt-bindings-clock-Add-cpg-for-the-Renesas-RZ-T2H-SoC/20250226-221033
base: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty.git tty-testing
patch link: https://lore.kernel.org/r/20250226130935.3029927-7-thierry.bultel.yh%40bp.renesas.com
patch subject: [PATCH v3 06/13] clk: renesas: Add support for R9A09G077 SoC
config: arc-randconfig-r122-20250227 (https://download.01.org/0day-ci/archive/20250228/202502280006.8lJfdpzm-lkp@intel.com/config)
compiler: arceb-elf-gcc (GCC) 13.2.0
reproduce: (https://download.01.org/0day-ci/archive/20250228/202502280006.8lJfdpzm-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@...el.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202502280006.8lJfdpzm-lkp@intel.com/
sparse warnings: (new ones prefixed by >>)
>> drivers/clk/renesas/renesas-cpg-mssr.c:216:49: sparse: sparse: incorrect type in initializer (different address spaces) @@ expected void *base @@ got void [noderef] __iomem * @@
drivers/clk/renesas/renesas-cpg-mssr.c:216:49: sparse: expected void *base
drivers/clk/renesas/renesas-cpg-mssr.c:216:49: sparse: got void [noderef] __iomem *
>> drivers/clk/renesas/renesas-cpg-mssr.c:294:51: sparse: sparse: incorrect type in initializer (different address spaces) @@ expected void [noderef] __iomem *addr @@ got void * @@
drivers/clk/renesas/renesas-cpg-mssr.c:294:51: sparse: expected void [noderef] __iomem *addr
drivers/clk/renesas/renesas-cpg-mssr.c:294:51: sparse: got void *
vim +216 drivers/clk/renesas/renesas-cpg-mssr.c
211
212 static void *cpg_rzt2h_addr_from_offset(struct clk_hw *hw, u16 offset)
213 {
214 struct mstp_clock *clock = to_mstp_clock(hw);
215 struct cpg_mssr_priv *priv = clock->priv;
> 216 void *base = RZT2H_MSTPCR_BLOCK(offset) ? priv->pub.base1 : priv->pub.base0;
217
218 return base + RZT2H_MSTPCR_OFFSET(offset);
219 }
220
221 static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable)
222 {
223 struct mstp_clock *clock = to_mstp_clock(hw);
224 struct cpg_mssr_priv *priv = clock->priv;
225 unsigned int reg = clock->index / 32;
226 unsigned int bit = clock->index % 32;
227 struct device *dev = priv->dev;
228 u32 bitmask = BIT(bit);
229 unsigned long flags;
230 u32 value;
231 int error;
232
233 dev_dbg(dev, "MSTP %u%02u/%pC %s\n", reg, bit, hw->clk,
234 enable ? "ON" : "OFF");
235 spin_lock_irqsave(&priv->pub.rmw_lock, flags);
236
237 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A) {
238 value = readb(priv->pub.base0 + priv->control_regs[reg]);
239 if (enable)
240 value &= ~bitmask;
241 else
242 value |= bitmask;
243 writeb(value, priv->pub.base0 + priv->control_regs[reg]);
244
245 /* dummy read to ensure write has completed */
246 readb(priv->pub.base0 + priv->control_regs[reg]);
247 barrier_data(priv->pub.base0 + priv->control_regs[reg]);
248
249 } else {
250 value = readl(priv->pub.base0 + priv->control_regs[reg]);
251 if (enable)
252 value &= ~bitmask;
253 else
254 value |= bitmask;
255 writel(value, priv->pub.base0 + priv->control_regs[reg]);
256 }
257
258 spin_unlock_irqrestore(&priv->pub.rmw_lock, flags);
259
260 if (!enable || priv->reg_layout == CLK_REG_LAYOUT_RZ_A ||
261 priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H)
262 return 0;
263
264 error = readl_poll_timeout_atomic(priv->pub.base0 + priv->status_regs[reg],
265 value, !(value & bitmask), 0, 10);
266 if (error)
267 dev_err(dev, "Failed to enable SMSTP %p[%d]\n",
268 priv->pub.base0 + priv->control_regs[reg], bit);
269
270 return error;
271 }
272
273 static int cpg_mstp_clock_enable(struct clk_hw *hw)
274 {
275 return cpg_mstp_clock_endisable(hw, true);
276 }
277
278 static void cpg_mstp_clock_disable(struct clk_hw *hw)
279 {
280 cpg_mstp_clock_endisable(hw, false);
281 }
282
283 static int cpg_mstp_clock_is_enabled(struct clk_hw *hw)
284 {
285 struct mstp_clock *clock = to_mstp_clock(hw);
286 struct cpg_mssr_priv *priv = clock->priv;
287 unsigned int reg = clock->index / 32;
288 u32 value;
289
290 if (priv->reg_layout == CLK_REG_LAYOUT_RZ_A)
291 value = readb(priv->pub.base0 + priv->control_regs[reg]);
292 else if (priv->reg_layout == CLK_REG_LAYOUT_RZ_T2H) {
293 void __iomem *addr =
> 294 cpg_rzt2h_addr_from_offset(hw,
295 priv->control_regs[reg]);
296 value = readw(addr);
297 }
298 else
299 value = readl(priv->pub.base0 + priv->status_regs[reg]);
300
301 return !(value & BIT(clock->index % 32));
302 }
303
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
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