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Message-ID: <Z8C57rzRt90obAFg@gmail.com>
Date: Thu, 27 Feb 2025 20:15:58 +0100
From: Ingo Molnar <mingo@...nel.org>
To: "Chang S. Bae" <chang.seok.bae@...el.com>
Cc: linux-kernel@...r.kernel.org, x86@...nel.org, tglx@...utronix.de,
mingo@...hat.com, bp@...en8.de, dave.hansen@...ux.intel.com,
Linus Torvalds <torvalds@...ux-foundation.org>
Subject: Re: [PATCH RFC v1 00/11] x86: Support Intel Advanced Performance
Extensions
* Chang S. Bae <chang.seok.bae@...el.com> wrote:
> == Introduction ==
>
> APX introduces a new set of general-purpose registers designed to improve
> performance. Currently, these registers are expected to be used primarily
> by userspace applications, with no intended use in kernel mode. More
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> details on its use cases can be found in the published documentation [1].
I strongly suspect this won't remain so, unless there's some horrible
ISA limitation or other quirk that makes APX unsuitable for kernel use.
The moment one of the mainstream compilers adds support for it we'll
want to enable it for the kernel too. Since the new GP registers are
caller-saved they are fairly easy to use as scratch registers to reduce
stack pressure, which is very much present on x86-64, especially when
the frame pointer is in use.
So we need to keep that in mind when shaping these patches.
Unless I'm missing something that is. :-)
Thanks,
Ingo
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