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Message-ID: <20250227192536.2426490-2-dingwei@marvell.com>
Date: Thu, 27 Feb 2025 11:25:34 -0800
From: Wilson Ding <dingwei@...vell.com>
To: <linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>
CC: <andrew@...n.ch>, <gregory.clement@...tlin.com>,
<sebastian.hesselbarth@...il.com>, <robh@...nel.org>,
<krzk+dt@...nel.org>, <conor+dt@...nel.org>, <p.zabel@...gutronix.de>,
<salee@...vell.com>, <gakula@...vell.com>,
Wilson Ding <dingwei@...vell.com>
Subject: [PATCH v3 1/3] dt-bindings: reset: Add Armada8K reset controller
Add device-tree binding documentation for the Armada8K reset driver and
create the new head file for the reset line index definitions.
Signed-off-by: Wilson Ding <dingwei@...vell.com>
---
.../reset/marvell,armada8k-reset.yaml | 48 +++++++++++++++++++
.../reset/marvell,armada8k-reset.h | 27 +++++++++++
2 files changed, 75 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/marvell,armada8k-reset.yaml
create mode 100644 include/dt-bindings/reset/marvell,armada8k-reset.h
diff --git a/Documentation/devicetree/bindings/reset/marvell,armada8k-reset.yaml b/Documentation/devicetree/bindings/reset/marvell,armada8k-reset.yaml
new file mode 100644
index 000000000000..9af352f528de
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/marvell,armada8k-reset.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2025 Wilson Ding <dingwei@...vell.com>
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/reset/marvell,armada8k-reset.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Marvell Armada8K reset controller
+
+maintainers:
+ - Wilson Ding <dingwei@...vell.com>
+
+description: The reset controller node must be a sub-node of the system
+ controller node on Armada7K/8K or CN913x SoCs.
+
+properties:
+ compatible:
+ const: marvell,armada8k-reset
+
+ reg:
+ description:
+ The register offset (to syscon register address) and size
+ maxItems: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ syscon0: system-controller@...000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x440000 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ swrst: reset-controller@268 {
+ compatible = "marvell,armada8k-reset";
+ reg = <0x268 0x4>;
+ #reset-cells = <1>;
+ };
+ };
diff --git a/include/dt-bindings/reset/marvell,armada8k-reset.h b/include/dt-bindings/reset/marvell,armada8k-reset.h
new file mode 100644
index 000000000000..18c6f4f761e2
--- /dev/null
+++ b/include/dt-bindings/reset/marvell,armada8k-reset.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2025, Marvell. All Rights Reserved.
+ */
+
+#ifndef _DT_BINDINGS_MARVELL_ARMADA8K_RESET_H_
+#define _DT_BINDINGS_MARVELL_ARMADA8K_RESET_H_
+
+#define CP110_RESET_AUDIO 0
+#define CP110_RESET_TDM 1
+#define CP110_RESET_ICU 2
+#define CP110_RESET_PP2 3
+#define CP110_RESET_SDIO 4
+#define CP110_RESET_XOR1 7
+#define CP110_RESET_XOR0 8
+#define CP110_RESET_PCIE0_X1 11
+#define CP110_RESET_PCIE1_X1 12
+#define CP110_RESET_PCIE_X4 13
+#define CP110_RESET_SATA 15
+#define CP110_RESET_USB3_HOST0 22
+#define CP110_RESET_USB3_HOST1 23
+#define CP110_RESET_USB3_DEV 24
+#define CP110_RESET_EIP150F 25
+#define CP110_RESET_EIP197 26
+#define CP110_RESET_MSS 29
+
+#endif /* _DT_BINDINGS_MARVELL_ARMADA8K_RESET_H_ */
--
2.43.0
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