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Message-ID: <20250227202206.2551305-2-c-vankar@ti.com>
Date: Fri, 28 Feb 2025 01:52:05 +0530
From: Chintan Vankar <c-vankar@...com>
To: Conor Dooley <conor+dt@...nel.org>,
        Krzysztof Kozlowski
	<krzk+dt@...nel.org>,
        Rob Herring <robh@...nel.org>, Peter Rosin
	<peda@...ntia.se>,
        <tglx@...utronix.de>, <gregkh@...uxfoundation.org>, <vigneshr@...com>,
        <nm@...com>, <s-vadapalli@...com>, <danishanwar@...com>
CC: <linux-kernel@...r.kernel.org>, <devicetree@...r.kernel.org>,
        <c-vankar@...com>
Subject: [RFC PATCH 1/2] devicetree: bindings: mux: reg-mux: Update bindings for reg-mux for new property

DT-binding of reg-mux is defined in such a way that one need to provide
register offset and mask in a "mux-reg-masks" property and corresponding
register value in "idle-states" property. This constraint forces to define
these values in such a way that "mux-reg-masks" and "idle-states" must be
in sync with each other. This implementation would be more complex if
specific register or set of registers need to be configured which has
large memory space. Introduce a new property "mux-reg-masks-state" which
allow to specify offset, mask and value as a tuple in a single property.

Signed-off-by: Chintan Vankar <c-vankar@...com>
---
 .../devicetree/bindings/mux/reg-mux.yaml      | 29 +++++++++++++++++--
 1 file changed, 27 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/mux/reg-mux.yaml b/Documentation/devicetree/bindings/mux/reg-mux.yaml
index dc4be092fc2f..a73c5efcf860 100644
--- a/Documentation/devicetree/bindings/mux/reg-mux.yaml
+++ b/Documentation/devicetree/bindings/mux/reg-mux.yaml
@@ -32,11 +32,36 @@ properties:
         - description: pre-shifted bitfield mask
     description: Each entry pair describes a single mux control.
 
-  idle-states: true
+  idle-states:
+    description: Each entry describes mux register state.
+
+  mux-reg-masks-state:
+    $ref: /schemas/types.yaml#/definitions/uint32-matrix
+    items:
+      items:
+        - description: register offset
+        - description: pre-shifted bitfield mask
+        - description: register value to be set
+    description: This property is an extension of mux-reg-masks which
+                 allows specifying register offset, mask and register
+                 value to be set in a single property.
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - reg-mux
+              - mmio-mux
+    then:
+      properties:
+        mux-reg-masks: true
+        mux-reg-masks-state: true
+      maxItems: 1
 
 required:
   - compatible
-  - mux-reg-masks
   - '#mux-control-cells'
 
 additionalProperties: false
-- 
2.34.1


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