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Message-ID: <20250227215732.5f5753d9@minigeek.lan>
Date: Thu, 27 Feb 2025 21:57:32 +0000
From: Andre Przywara <andre.przywara@....com>
To: Andras Szemzo <szemzo.andras@...il.com>
Cc: Michael Turquette <mturquette@...libre.com>, Stephen Boyd
<sboyd@...nel.org>, Rob Herring <robh@...nel.org>, Krzysztof Kozlowski
<krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, Chen-Yu Tsai
<wens@...e.org>, Jernej Skrabec <jernej.skrabec@...il.com>, Samuel Holland
<samuel@...lland.org>, Linus Walleij <linus.walleij@...aro.org>, Philipp
Zabel <p.zabel@...gutronix.de>, Maxime Ripard <mripard@...nel.org>, Vinod
Koul <vkoul@...nel.org>, Kishon Vijay Abraham I <kishon@...nel.org>, Ulf
Hansson <ulf.hansson@...aro.org>, Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>, Uwe
Kleine-König <u.kleine-koenig@...libre.com>, Florian
Fainelli <florian.fainelli@...adcom.com>, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-sunxi@...ts.linux.dev, linux-kernel@...r.kernel.org,
linux-phy@...ts.infradead.org, linux-gpio@...r.kernel.org,
linux-pm@...r.kernel.org, linux-riscv@...ts.infradead.org
Subject: Re: [PATCH v2 02/10] pinctrl: sunxi: add driver for Allwinner V853
On Wed, 5 Feb 2025 13:52:17 +0100
Andras Szemzo <szemzo.andras@...il.com> wrote:
Hi,
> The V853 family has multiple package variants, from BGA to QFN88.
> The latter has co-packaged DRAM and fewer pins, and less features (pin muxes).
> All family members can be supported by a single driver, as the available pins
> with allowed muxes is the same across the devices.
>
> This new pinctrl driver depends on the new sunxi device-tree based mux support
> patch series [1].
>
> [1]: https://lore.kernel.org/linux-sunxi/20241111005750.13071-1-andre.przywara@arm.com/T/
>
> Signed-off-by: Andras Szemzo <szemzo.andras@...il.com>
> ---
> drivers/pinctrl/sunxi/Kconfig | 5 ++
> drivers/pinctrl/sunxi/Makefile | 1 +
> drivers/pinctrl/sunxi/pinctrl-sun8i-v853.c | 53 ++++++++++++++++++++++
> 3 files changed, 59 insertions(+)
> create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun8i-v853.c
>
> diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
> index a78fdbbdfc0c..fac9c61039e2 100644
> --- a/drivers/pinctrl/sunxi/Kconfig
> +++ b/drivers/pinctrl/sunxi/Kconfig
> @@ -81,6 +81,11 @@ config PINCTRL_SUN9I_A80_R
> default MACH_SUN9I
> select PINCTRL_SUNXI
>
> +config PINCTRL_SUN8I_V853
> + bool "Support for the Allwinner V853/V851S/V851SE PIO"
> + default MACH_SUN8I
> + select PINCTRL_SUNXI
> +
> config PINCTRL_SUN20I_D1
> bool "Support for the Allwinner D1 PIO"
> default MACH_SUN8I || (RISCV && ARCH_SUNXI)
> diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
> index 2ff5a55927ad..8937b56b2ef4 100644
> --- a/drivers/pinctrl/sunxi/Makefile
> +++ b/drivers/pinctrl/sunxi/Makefile
> @@ -20,6 +20,7 @@ obj-$(CONFIG_PINCTRL_SUN8I_A83T_R) += pinctrl-sun8i-a83t-r.o
> obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o
> obj-$(CONFIG_PINCTRL_SUN8I_H3_R) += pinctrl-sun8i-h3-r.o
> obj-$(CONFIG_PINCTRL_SUN8I_V3S) += pinctrl-sun8i-v3s.o
> +obj-$(CONFIG_PINCTRL_SUN8I_V853) += pinctrl-sun8i-v853.o
> obj-$(CONFIG_PINCTRL_SUN20I_D1) += pinctrl-sun20i-d1.o
> obj-$(CONFIG_PINCTRL_SUN50I_H5) += pinctrl-sun50i-h5.o
> obj-$(CONFIG_PINCTRL_SUN50I_H6) += pinctrl-sun50i-h6.o
> diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-v853.c b/drivers/pinctrl/sunxi/pinctrl-sun8i-v853.c
> new file mode 100644
> index 000000000000..fb2112ee12d0
> --- /dev/null
> +++ b/drivers/pinctrl/sunxi/pinctrl-sun8i-v853.c
> @@ -0,0 +1,53 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Allwinner V853 SoC pinctrl driver.
> + *
> + * Copyright (c) 2025 Andras Szemzo <szemzo.andras@...il.com>
> + */
> +
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/pinctrl/pinctrl.h>
> +
> +#include "pinctrl-sunxi.h"
> +
> +static const u8 v853_nr_bank_pins[SUNXI_PINCTRL_MAX_BANKS] =
> +/* PA PB PC PD PE PF PG PH PI */
> + { 22, 0, 12, 23, 18, 7, 8, 16, 5 };
> +
> +static const unsigned int v853_irq_bank_map[] = { 0, 2, 3, 4, 5, 6, 7, 8 };
> +
> +static const u8 v853_irq_bank_muxes[SUNXI_PINCTRL_MAX_BANKS] =
> +/* PA PB PC PD PE PF PG PH PI */
> + { 14, 0, 14, 14, 14, 14, 14, 14, 14 };
> +
> +static struct sunxi_pinctrl_desc v853_pinctrl_data = {
> + .irq_banks = ARRAY_SIZE(v853_irq_bank_map),
> + .irq_bank_map = v853_irq_bank_map,
> + .io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,
> +};
> +
> +static int v853_pinctrl_probe(struct platform_device *pdev)
> +{
> + return sunxi_pinctrl_dt_table_init(pdev, v853_nr_bank_pins,
> + v853_irq_bank_muxes,
> + &v853_pinctrl_data,
> + SUNXI_PINCTRL_NEW_REG_LAYOUT |
> + SUNXI_PINCTRL_ELEVEN_BANKS);
This last flag doesn't apply: it would put the offset for the
POW_MOD_SEL registers at 0x380, but the manual says it's 0x340, as with
the previous SoCs.
I compared the rest against the A523 driver, and the V853 specific bits
against the manual: they match, so with that line removed:
Reviewed-by: Andre Przywara <andre.przywara@....com>
Cheers,
Andre
> +}
> +
> +static const struct of_device_id v853_pinctrl_match[] = {
> + { .compatible = "allwinner,sun8i-v853-pinctrl", },
> + {}
> +};
> +
> +static struct platform_driver v853_pinctrl_driver = {
> + .probe = v853_pinctrl_probe,
> + .driver = {
> + .name = "sun8i-v853-pinctrl",
> + .of_match_table = v853_pinctrl_match,
> + },
> +};
> +builtin_platform_driver(v853_pinctrl_driver);
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