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Date: Thu, 27 Feb 2025 08:19:20 +0000
From: Ryan Chen <ryan_chen@...eedtech.com>
To: Krzysztof Kozlowski <krzk@...nel.org>
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Subject: RE: [PATCH v16 1/3] dt-bindings: i2c: aspeed: support for
 AST2600-i2cv2

> Subject: Re: [PATCH v16 1/3] dt-bindings: i2c: aspeed: support for
> AST2600-i2cv2
> 
> On 26/02/2025 10:28, Ryan Chen wrote:
> >> Subject: Re: [PATCH v16 1/3] dt-bindings: i2c: aspeed: support for
> >> AST2600-i2cv2
> >>
> >> On Mon, Feb 24, 2025 at 01:59:34PM +0800, Ryan Chen wrote:
> >>> Add ast2600-i2cv2 compatible and aspeed,global-regs,
> >>> aspeed,enable-dma and description for ast2600-i2cv2.
> >>>
> >>> Signed-off-by: Ryan Chen <ryan_chen@...eedtech.com>
> >>> ---
> >>>  .../devicetree/bindings/i2c/aspeed,i2c.yaml   | 58
> +++++++++++++++++++
> >>>  1 file changed, 58 insertions(+)
> >>>
> >>> diff --git a/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml
> >>> b/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml
> >>> index 5b9bd2feda3b..356033d18f90 100644
> >>> --- a/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml
> >>> +++ b/Documentation/devicetree/bindings/i2c/aspeed,i2c.yaml
> >>> @@ -44,12 +44,60 @@ properties:
> >>>      description: frequency of the bus clock in Hz defaults to 100
> >>> kHz when
> >> not
> >>>        specified
> >>>
> >>> +  multi-master:
> >>> +    type: boolean
> >>> +    description:
> >>> +      states that there is another master active on this bus
> >>
> >> Except that this wasn't ever tested...
> >>
> >> Don't duplicate properties. i2c-controller schema has it already.
> >
> > I will remove it to avoid duplication.
> >>
> >>> +
> >>> +  aspeed,enable-dma:
> >>> +    type: boolean
> >>> +    description: |
> >>> +      I2C bus enable dma mode transfer.
> >>> +
> >>> +      ASPEED ast2600 platform equipped with 16 I2C controllers that
> >> share a
> >>> +      single DMA engine. DTS files can specify the data transfer
> >>> + mode
> >> to/from
> >>> +      the device, either DMA or programmed I/O. However, hardware
> >>> + limitations
> >>
> >> so what is byte mode?
> > I explain in cover, I will add here also.
> 
> Cover letters do not get merged and we do not read them, except when looking
> for dependencies and explanations of process (like RFC). Your hardware
> description must be fully contained in commits, not cover letter.

Got it, I will paste it in commits. 
> 
> 
> > aspeed,enable-byte:
> > Force i2c controller use byte mode transfer. the byte mode transfer
> > will send i2c data each byte by byte, inlcude address read/write.
> 
> Isn't this standard FIFO mode?
Yes, it is.
> 
> Why anyone would need to enable byte mode for given board?
By default, it is buffer-mode, for performance, I don't want user enable byte-mode, it will increase CPU utilize.
But someone want to be force enable byte-mode, so I add properties. 
https://patchwork.ozlabs.org/project/linux-aspeed/patch/20241007035235.2254138-3-ryan_chen@aspeedtech.com/
> 
> >
> >>
> >>> +      may require a DTS to manually allocate which controller can
> >>> + use
> >> DMA mode.
> >>> +      The "aspeed,enable-dma" property allows control of this.
> >>> +
> >>> +      In cases where one the hardware design results in a specific
> >>> +      controller handling a larger amount of data, a DTS would likely
> >>> +      enable DMA mode for that one controller.
> >>> +
> >>> +  aspeed,enable-byte:
> >>> +    type: boolean
> >>> +    description: |
> >>> +      I2C bus enable byte mode transfer.
> >>
> >> No, either this is expressed as lack of dma mode property or if you
> >> have three modes, then rather some enum (aspeed,transfer-mode ?)
> >
> > Thanks suggestion, I will using an enum property like aspeed,transfer-mode
> instead.
> >>
> >>
> >>
> >>> +
> >>> +  aspeed,global-regs:
> >>> +    $ref: /schemas/types.yaml#/definitions/phandle
> >>> +    description: The phandle of i2c global register node.
> >>
> >> For what? Same question as usual: do not repeat property name, but
> >> say what is this used for and what exactly it points to.
> >>
> >> s/i2c/I2C/ but then what is "I2C global register node"? This is how
> >> you call your device in datasheet?
> >>
> > I do descript in cover, should add into the yaml file ?
> 
> 
> Again, cover letter does not matter. Your hardware must be explained here.
Will add into commit. 
> 
> >
> > aspeed,global-regs:
> > This global register is needed, global register is setting for new
> > clock divide control, and new register set control.
> 
> So this means you implement clock controller via syscon?
No, it is just mode switch. It also explain in cover. I will add it in commit. 
The legacy register layout is mix controller/target register control together. The following is add more detail description about new register layout. And new feature set add for register.
> 
> >
> >>
> >>> +
> >>>  required:
> >>>    - reg
> >>>    - compatible
> >>>    - clocks
> >>>    - resets
> >>>
> >>> +allOf:
> >>> +  - $ref: /schemas/i2c/i2c-controller.yaml#
> >>> +  - if:
> >>> +      properties:
> >>> +        compatible:
> >>> +          contains:
> >>> +            const: aspeed,ast2600-i2cv2
> >>
> >> NAK, undocumented compatible.
> >
> > Sorry, I should add what kind of document about this compatible?
> 
> You cannot add new compatibles without documenting them. Documentation
> is in the form of DT schema and each compatible must be listed (in some
> way) in compatible property description.

Sorry, do you mean, I add following in yaml or commit message?

This series add AST2600 i2cv2 new register set driver. The i2cv2 driver is new register set that have new clock divider option for more flexiable generation. And also have separate i2c controller and target register set for control, patch #2 is i2c controller driver only, patch #3 is add i2c target mode driver.

The legacy register layout is mix controller/target register control together. The following is add more detail description about new register layout. And new feature set add for register.

-Add new clock divider option for more flexible and accurate clock rate generation -Add tCKHighMin timing to guarantee SCL high pulse width.
-Add support dual pool buffer mode, split 32 bytes pool buffer of each device into 2 x 16 bytes for Tx and Rx individually.
-Increase DMA buffer size to 4096 bytes and support byte alignment.
-Re-define the base address of BUS1 ~ BUS16 and Pool buffer.
-Re-define registers for separating controller and target mode control.
-Support 4 individual DMA buffers for controller Tx and Rx, target Tx and Rx.

> 
> 
> Best regards,
> Krzysztof

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