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Message-ID: <20250226121838.364533-4-LeoLiu-oc@zhaoxin.com> Date: Wed, 26 Feb 2025 20:18:37 +0800 From: LeoLiu-oc <LeoLiu-oc@...oxin.com> To: <rafael@...nel.org>, <lenb@...nel.org>, <james.morse@....com>, <tony.luck@...el.com>, <bp@...en8.de>, <bhelgaas@...gle.com>, <robert.moore@...el.com>, <yazen.ghannam@....com>, <avadhut.naik@....com>, <linux-acpi@...r.kernel.org>, <linux-kernel@...r.kernel.org>, <linux-pci@...r.kernel.org>, <acpica-devel@...ts.linux.dev> CC: <CobeChen@...oxin.com>, <TonyWWang@...oxin.com>, <ErosZhang@...oxin.com>, <leoliu@...oxin.com>, LeoLiuoc <LeoLiu-oc@...oxin.com> Subject: [PATCH v5 3/4] PCI: Add AER bits #defines for PCIe to PCI/PCI-X Bridge From: LeoLiuoc <LeoLiu-oc@...oxin.com> Define secondary uncorrectable error mask register, secondary uncorrectable error severity register and secondary error capabilities and control register bits in AER capability for PCIe to PCI/PCI-X Bridge. Please refer to PCIe to PCI/PCI-X Bridge Specification r1.0, sec 5.2.3.2, 5.2.3.3 and 5.2.3.4. Signed-off-by: LeoLiuoc <LeoLiu-oc@...oxin.com> --- include/uapi/linux/pci_regs.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 3445c4970e4d..0566c663beb7 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -812,6 +812,10 @@ #define PCI_ERR_ROOT_ERR_SRC 0x34 /* Error Source Identification */ #define PCI_ERR_PREFIX_LOG 0x38 /* TLP Prefix LOG Register (up to 16 bytes) */ +#define PCI_ERR_UNCOR_MASK2 0x30 /* PCIe to PCI/PCI-X Bridge */ +#define PCI_ERR_UNCOR_SEVER2 0x34 /* PCIe to PCI/PCI-X Bridge */ +#define PCI_ERR_CAP2 0x38 /* PCIe to PCI/PCI-X Bridge */ + /* Virtual Channel */ #define PCI_VC_PORT_CAP1 0x04 #define PCI_VC_CAP1_EVCC 0x00000007 /* extended VC count */ -- 2.34.1
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