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Message-ID: <a26g7pt3pll5d6jmkucdychrectbaa27ft65cuw7mrlirupx63@ijeqgow2s4ij>
Date: Thu, 27 Feb 2025 11:39:49 +0100
From: Thierry Reding <thierry.reding@...il.com>
To: Vishwaroop A <va@...dia.com>
Cc: jonathanh@...dia.com, skomatineni@...dia.com, ldewangan@...dia.com,
broonie@...nel.org, linux-spi@...r.kernel.org, linux-tegra@...r.kernel.org,
linux-kernel@...r.kernel.org, kyarlagadda@...dia.com, smangipudi@...dia.com
Subject: Re: [PATCH v2 1/6] arm64: tegra: Configure QSPI clocks and add DMA
On Wed, Feb 12, 2025 at 02:46:46PM +0000, Vishwaroop A wrote:
> Set QSPI0_2X_PM to 199.99 MHz and QSPI0_PM to 99.99 MHz using
> PLLC as the parent clock. These frequencies allow Quad IO DT
> reads up to 99.99 MHz, which is the fastest that can be
> achieved considering various PLL and clock divider constraints.
>
> Populate the DMA and IOMMU properties for the Tegra234 QSPI devices to
> enable DMA support.
>
> Signed-off-by: Vishwaroop A <va@...dia.com>
> ---
> arch/arm64/boot/dts/nvidia/tegra234.dtsi | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/nvidia/tegra234.dtsi b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> index 2601b43b2d8c..0ac2d3aba930 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> +++ b/arch/arm64/boot/dts/nvidia/tegra234.dtsi
> @@ -2948,6 +2948,13 @@
> <&bpmp TEGRA234_CLK_QSPI0_PM>;
> clock-names = "qspi", "qspi_out";
> resets = <&bpmp TEGRA234_RESET_QSPI0>;
> + assigned-clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>,
> + <&bpmp TEGRA234_CLK_QSPI0_PM>;
> + assigned-clock-rates = <199999999 99999999>;
> + assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC>;
> + dma-names = "rx", "tx";
Other than the dma-names property which was already discussed, this
looks fine.
Thierry
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