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Message-ID: <20250228-copilot-trekker-72a20709e9f7@spud>
Date: Fri, 28 Feb 2025 18:28:27 +0000
From: Conor Dooley <conor@...nel.org>
To: iansdannapel@...il.com
Cc: linux-fpga@...r.kernel.org, Moritz Fischer <mdf@...nel.org>,
Wu Hao <hao.wu@...el.com>, Xu Yilun <yilun.xu@...el.com>,
Tom Rix <trix@...hat.com>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Neil Armstrong <neil.armstrong@...aro.org>,
Jonathan Cameron <Jonathan.Cameron@...wei.com>,
Rafał Miłecki <rafal@...ecki.pl>,
Aradhya Bhatia <a-bhatia1@...com>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@...r.kernel.org>,
open list <linux-kernel@...r.kernel.org>
Subject: Re: [v4 2/3] dt-bindings: fpga: Add Efinix SPI programming bindings
On Fri, Feb 28, 2025 at 10:47:31AM +0100, iansdannapel@...il.com wrote:
> From: Ian Dannapel <iansdannapel@...il.com>
>
> Add device tree bindings documentation for configuring Efinix FPGA
> using serial SPI passive programming mode.
>
> Signed-off-by: Ian Dannapel <iansdannapel@...il.com>
> ---
> .../devicetree/bindings/fpga/efinix,spi.yaml | 81 +++++++++++++++++++
> 1 file changed, 81 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/fpga/efinix,spi.yaml
>
> diff --git a/Documentation/devicetree/bindings/fpga/efinix,spi.yaml b/Documentation/devicetree/bindings/fpga/efinix,spi.yaml
> new file mode 100644
> index 000000000000..145c96f38e45
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/fpga/efinix,spi.yaml
Filename matching a compatible please.
> @@ -0,0 +1,81 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/fpga/efinix,spi.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Efinix SPI FPGA Manager
> +
> +maintainers:
> + - Ian Dannapel <iansdannapel@...il.com>
> +
> +description: |
> + Efinix FPGAs (Trion, Topaz, and Titanium families) support loading bitstreams
> + through "SPI Passive Mode".
> + Note 1: Only bus width 1x is supported.
> + Note 2: Additional pins hogs for bus width configuration must be set
> + elsewhere, if necessary.
> + Note 3: Topaz and Titanium support is based on documentation but remains
> + untested.
Points 1 and 3 here seem to be driver limitations, and shouldn't really
be present in a document describing the hardware?
> +
> + References:
> + - https://www.efinixinc.com/docs/an006-configuring-trion-fpgas-v6.3.pdf
> + - https://www.efinixinc.com/docs/an033-configuring-titanium-fpgas-v2.8.pdf
> + - https://www.efinixinc.com/docs/an061-configuring-topaz-fpgas-v1.1.pdf
> +
> +allOf:
> + - $ref: /schemas/spi/spi-peripheral-props.yaml#
> +
> +properties:
> + compatible:
> + enum:
> + - efinix,trion-spi
> + - efinix,titanium-spi
> + - efinix,topaz-spi
> + - efinix,fpga-spi
What hardware does this device represent? Other ones are obvious matches
to the families you mention, but what is this one?
Cheers,
Conor.
> +
> + spi-cpha: true
> +
> + spi-cpol: true
> +
> + spi-max-frequency:
> + maximum: 25000000
> +
> + reg:
> + maxItems: 1
> +
> + reset-gpios:
> + description:
> + reset and re-configuration trigger pin (low active)
> + maxItems: 1
> +
> + cdone-gpios:
> + description:
> + optional configuration done status pin (high active)
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - reset-gpios
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/gpio/gpio.h>
> + spi {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
> + fpga-mgr@0 {
> + compatible = "efinix,trion-spi";
> + reg = <0>;
> + spi-max-frequency = <25000000>;
> + spi-cpha;
> + spi-cpol;
> + reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
> + cdone-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
> + };
> + };
> +...
> --
> 2.43.0
>
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