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Message-ID:
 <PN0PR01MB91667A6458D213413AB64E91FECC2@PN0PR01MB9166.INDPRD01.PROD.OUTLOOK.COM>
Date: Fri, 28 Feb 2025 15:32:38 +0800
From: Chen Wang <unicorn_wang@...look.com>
To: Yixun Lan <dlan@...too.org>, Zixian Zeng <sycamoremoon376@...il.com>
Cc: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
 Conor Dooley <conor+dt@...nel.org>, Paul Walmsley
 <paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>,
 Albert Ou <aou@...s.berkeley.edu>, Inochi Amaoto <inochiama@...look.com>,
 devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org,
 linux-kernel@...r.kernel.org, sophgo@...ts.linux.dev
Subject: Re: [PATCH] riscv: dts: sophgo: sg2042: Add spi devices

Aside comments from Yixuan, appending more ...

Change title to: "[PATCH] riscv: sophgo: dts: Add spi controller for SG2042"

The prefix sequence is required from my previous review experience, and 
we are adding controller node.

On 2025/2/28 11:55, Yixun Lan wrote:
> Hi Zixian:
>
> On 10:47 Fri 28 Feb     , Zixian Zeng wrote:
>> Add spi devices for the sg2042 soc.
Change to:

```
Add spi controllers for SG2042.


SG2042 uses the upstreamed Synopsys DW SPI IP.

```

This way, everyone can better understand why "snps,dw-apb-ssi" is used 
in the code.
>>
>> Signed-off-by: Zixian Zeng <sycamoremoon376@...il.com>
>> ---
>>   arch/riscv/boot/dts/sophgo/sg2042.dtsi | 30 ++++++++++++++++++++++++++++++
>>   1 file changed, 30 insertions(+)
>>
>> diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
>> index 0fca16c469cc95aa897b6b57e0a287a687b4d251..d413daa47cf081f23284851db1eeceb3a157e9c0 100644
>> --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
>> +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
>> @@ -800,5 +800,35 @@ flash@0 {
>>   				compatible = "jedec,spi-nor";
>>   			};
>>   		};
>> +
>> +		spi0: spi@...0004000 {
Order the nodes please, see 
https://docs.kernel.org/devicetree/bindings/dts-coding-style.html#order-of-nodes.
>> +			compatible = "snps,dw-apb-ssi";
>> +			#address-cells = <0x01>;
>> +			#size-cells = <0x00>;
>> +			reg = <0x70 0x40004000 0x00 0x1000>;
> for consistency, I'd suggest moving 'reg' info above '#address-cells'
>
>> +			interrupt-parent = <&intc>;
>> +			interrupts = <110 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&clkgen GATE_CLK_APB_SPI>,
>> +					<&clkgen GATE_CLK_SYSDMA_AXI>;
>> +			clock-frequency = <250000000>;

Have you run dtb check at your side before sending out the patch? I ran 
and got following errors:

```

/home/u/ws/dev-linux/out-linux/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dtb: 
spi@...0004000: Unevaluated properties are not allowed 
('clock-frequency' was unexpected)
     from schema $id: 
http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#
/home/u/ws/dev-linux/out-linux/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dtb: 
spi@...0005000: Unevaluated properties are not allowed 
('clock-frequency' was unexpected)
     from schema $id: 
http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#

```

You can run `make CHECK_DTBS=y W=1 sophgo/sg2042-milkv-pioneer.dtb`.


> ditto, move clock above interrupt
>
>> +			resets = <&rstgen RST_SPI0>;
>> +			num-cs = <0x02>;
>> +			status = "okay";
> in dtsi file, please make status disabled by default, then enable it at board file
>
>> +		};
>> +
>> +		spi1: spi@...0005000 {
>> +			compatible = "snps,dw-apb-ssi";
>> +			#address-cells = <0x01>;
>> +			#size-cells = <0x00>;
>> +			reg = <0x70 0x40005000 0x00 0x1000>;
>> +			interrupt-parent = <&intc>;
>> +			interrupts = <111 IRQ_TYPE_LEVEL_HIGH>;
>> +			clocks = <&clkgen GATE_CLK_APB_SPI>,
>> +					<&clkgen GATE_CLK_SYSDMA_AXI>;
>> +			clock-frequency = <250000000>;
>> +			resets = <&rstgen RST_SPI1>;
>> +			num-cs = <0x02>;
>> +			status = "okay";
>> +		};
>>   	};
>>   };
>>
>> ---
>> base-commit: 9ef5d3235d41a6f5230d3ddf5eb994483853b3e8
What's this base? I can not see it in lastest master. Make sure your 
patch is based on the lastest master or at least an official RC tag such 
as v6.14-rcX.
>> change-id: 20250228-sfg-spi-e3f2aeca09ab
>>
>> Best regards,
>> -- 
>> Zixian Zeng <sycamoremoon376@...il.com>
>>

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