linux-kernel - Re: [PATCH v3 1/3] arm64: dts: qcom: sm8650: fix PMU interrupt flag

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Message-ID: <9c15f084-ea4b-48e4-add6-c5b0c6de1155@linaro.org>
Date: Fri, 28 Feb 2025 09:07:51 +0100
From: Neil Armstrong <neil.armstrong@...aro.org>
To: Stephan Gerhold <stephan.gerhold@...aro.org>,
 Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Cc: Bjorn Andersson <andersson@...nel.org>,
 Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, linux-arm-msm@...r.kernel.org,
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 1/3] arm64: dts: qcom: sm8650: fix PMU interrupt flag

On 27/02/2025 19:48, Stephan Gerhold wrote:
> On Thu, Feb 27, 2025 at 06:50:31PM +0100, Konrad Dybcio wrote:
>> On 27.02.2025 5:04 PM, Neil Armstrong wrote:
>>> The ARM PMU interrupt is sometimes defined as IRQ_TYPE_LEVEL_LOW,
>>> or IRQ_TYPE_LEVEL_HIGH, but downstream and recent platforms used the
>>> IRQ_TYPE_LEVEL_HIGH flag so align the SM8650 definition to have a
>>> functional PMU working.
>>>
>>> Fixes: c8a346e408cb ("arm64: dts: qcom: Split PMU nodes for heterogeneous CPUs")
>>> Fixes: d2350377997f ("arm64: dts: qcom: add initial SM8650 dtsi")
>>> Signed-off-by: Neil Armstrong <neil.armstrong@...aro.org>
>>> ---
>>
>> I couldn't find anything to back this up, not inside, not on Arm's
>> website, but downstream agrees, so..
>>
> 
> The GIC doesn't really have a notion of LOW vs HIGH in the programmable
> registers. This is generally a design time parameter, e.g. for GIC-600:
> 
>    Level-sensitive PPI signals are active-LOW by default, as with
>    previous Arm GIC implementations. However, individual PPI signals can
>    be inverted and synchronized using parameters
>    gic600_<config_name>_PPI<ppi_id>_<cpu_number>_<ppi_number>_<INV/SYNC>.
> 
>    https://developer.arm.com/documentation/100336/0106/components-and-configuration/redistributor/redistributor-ppi-signals
> 
> For Linux it shouldn't really matter, because gic_configure_irq()
> ignores the polarity and looks only at IRQ_TYPE_LEVEL_MASK.
> 
> If you still want this to represent the actual truth, then all hints
> I can find only back this down (not up) I'm afraid:
> 
> Arm® Cortex®‑A520 Core Technical Reference Manual
> Arm® Cortex®-A720 Core Technical Reference Manual
> Arm® Cortex®-X4 Core Technical Reference Manual
> 
>    17.2 Performance monitors interrupts
>    When the PMU generates an interrupt, the nPMUIRQ[n] output is driven LOW.
> 
>    https://developer.arm.com/documentation/102517/0004/Performance-Monitors-Extension-support-/Performance-monitors-interrupts
>    https://developer.arm.com/documentation/102530/0002/Performance-Monitors-Extension-support-/Performance-monitors-interrupts
>    https://developer.arm.com/documentation/102484/0003/Performance-Monitors-Extension-support-/Performance-monitors-interrupts
> 
> So please check if this patch is really needed, otherwise I'd suggest
> dropping it.

Thanks a lot for looking into this !

I guess I'll drop this, and we may harmonize all qcom dtsi with LOW.

Neil

> 
> Thanks,
> Stephan