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Message-ID: <je4falvfemkemlvdfzdmgc7jx2gz6grpbmo6hwtpedjm7xi2gk@jr4frv3tn3l5>
Date: Fri, 28 Feb 2025 17:20:28 +0800
From: Inochi Amaoto <inochiama@...il.com>
To: Conor Dooley <conor@...nel.org>, Inochi Amaoto <inochiama@...il.com>
Cc: Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof Wilczyński <kw@...ux.com>, Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>,
Rob Herring <robh@...nel.org>, Bjorn Helgaas <bhelgaas@...gle.com>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Chen Wang <unicorn_wang@...look.com>, Philipp Zabel <p.zabel@...gutronix.de>,
Paul Walmsley <paul.walmsley@...ive.com>, Palmer Dabbelt <palmer@...belt.com>,
Albert Ou <aou@...s.berkeley.edu>, Niklas Cassel <cassel@...nel.org>,
Shashank Babu Chinta Venkata <quic_schintav@...cinc.com>, linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
sophgo@...ts.linux.dev, linux-kernel@...r.kernel.org, linux-riscv@...ts.infradead.org,
Yixun Lan <dlan@...too.org>, Longbin Li <looong.bin@...il.com>
Subject: Re: [PATCH 1/2] dt-bindings: pci: Add Sophgo SG2044 PCIe host
On Fri, Feb 28, 2025 at 04:46:22PM +0800, Inochi Amaoto wrote:
> On Fri, Feb 28, 2025 at 02:34:00PM +0800, Inochi Amaoto wrote:
> > On Tue, Feb 25, 2025 at 11:35:23PM +0000, Conor Dooley wrote:
> > > On Tue, Feb 25, 2025 at 07:48:59AM +0800, Inochi Amaoto wrote:
> > > > On Mon, Feb 24, 2025 at 06:54:51PM +0000, Conor Dooley wrote:
> > > > > On Sat, Feb 22, 2025 at 08:34:10AM +0800, Inochi Amaoto wrote:
> > > > > > On Fri, Feb 21, 2025 at 05:01:41PM +0000, Conor Dooley wrote:
> > > > > > > On Fri, Feb 21, 2025 at 09:37:55AM +0800, Inochi Amaoto wrote:
> > > > > > > > The pcie controller on the SG2044 is designware based with
> > > > > > > > custom app registers.
> > > > > > > >
> > > > > > > > Add binding document for SG2044 PCIe host controller.
> > > > > > > >
> > > > > > > > Signed-off-by: Inochi Amaoto <inochiama@...il.com>
> > > > > > > > ---
> > > > > > > > .../bindings/pci/sophgo,sg2044-pcie.yaml | 125 ++++++++++++++++++
> > > > > > > > 1 file changed, 125 insertions(+)
> > > > > > > > create mode 100644 Documentation/devicetree/bindings/pci/sophgo,sg2044-pcie.yaml
> > > > > > > >
> > > > > > > > diff --git a/Documentation/devicetree/bindings/pci/sophgo,sg2044-pcie.yaml b/Documentation/devicetree/bindings/pci/sophgo,sg2044-pcie.yaml
> > > > > > > > new file mode 100644
> > > > > > > > index 000000000000..040dabe905e0
> > > > > > > > --- /dev/null
> > > > > > > > +++ b/Documentation/devicetree/bindings/pci/sophgo,sg2044-pcie.yaml
> > > > > > > > @@ -0,0 +1,125 @@
> > > > > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > > > > > +%YAML 1.2
> > > > > > > > +---
> > > > > > > > +$id: http://devicetree.org/schemas/pci/sophgo,sg2044-pcie.yaml#
> > > > > > > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > > > > > > +
> > > > > > > > +title: DesignWare based PCIe Root Complex controller on Sophgo SoCs
> > > > > > > > +
> > > > > > > > +maintainers:
> > > > > > > > + - Inochi Amaoto <inochiama@...il.com>
> > > > > > > > +
> > > > > > > > +description: |+
> > > > > > > > + SG2044 SoC PCIe Root Complex controller is based on the Synopsys DesignWare
> > > > > > > > + PCIe IP and thus inherits all the common properties defined in
> > > > > > > > + snps,dw-pcie.yaml.
> > > > > > > > +
> > > > > > > > +allOf:
> > > > > > > > + - $ref: /schemas/pci/pci-host-bridge.yaml#
> > > > > > > > + - $ref: /schemas/pci/snps,dw-pcie.yaml#
> > > > > > > > +
> > > > > > > > +properties:
> > > > > > > > + compatible:
> > > > > > > > + const: sophgo,sg2044-pcie
> > > > > > > > +
> > > > > > > > + reg:
> > > > > > > > + items:
> > > > > > > > + - description: Data Bus Interface (DBI) registers
> > > > > > > > + - description: iATU registers
> > > > > > > > + - description: Config registers
> > > > > > > > + - description: Sophgo designed configuration registers
> > > > > > > > +
> > > > > > > > + reg-names:
> > > > > > > > + items:
> > > > > > > > + - const: dbi
> > > > > > > > + - const: atu
> > > > > > > > + - const: config
> > > > > > > > + - const: app
> > > > > > > > +
> > > > > > > > + clocks:
> > > > > > > > + items:
> > > > > > > > + - description: core clk
> > > > > > > > +
> > > > > > > > + clock-names:
> > > > > > > > + items:
> > > > > > > > + - const: core
> > > > > > > > +
> > > > > > > > + dma-coherent: true
> > > > > > >
> > > > > > > Why's this here? RISC-V is dma-coherent by default, with dma-noncoherent
> > > > > > > used to indicate systems/devices that are not.
> > > > > >
> > > > > > The PCIe is dma coherent, but the SoC itself is marked as
> > > > > > dma-noncoherent.
> > > > >
> > > > > By "the SoC itself", do you mean that the bus that this device is on is
> > > > > marked as dma-noncoherent?
> > > >
> > > > Yeah, I was told only PCIe device on SG2044 is dma coherent.
> > > > The others are not.
> > > >
> > > > > IMO, that should not be done if there are devices on it that are coherent.
> > > > >
> > > >
> > > > It is OK for me. But I wonder how to handle the non coherent device
> > > > in DT? Just Mark the bus coherent and mark all devices except the
> > > > PCIe device non coherent?
> > >
> > > Don't mark the bus anything (default is coherent) and mark the devices.
> >
> > I think this is OK for me.
> >
>
> In technical, I wonder a better way to "handle dma-noncoherent".
> In the binding check, all devices with this property complains
>
> "Unevaluated properties are not allowed ('dma-noncoherent' was unexpected)"
>
> It is a pain as at least 10 devices' binding need to be modified.
> So I wonder whether there is a way to simplify this.
>
Ignore this, I misunderstood the dma device. it seems like
only dmac and eth needs it.
Regards,
Inochi
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