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Message-ID: <202503020317.POudjwvT-lkp@intel.com>
Date: Sun, 2 Mar 2025 03:21:49 +0800
From: kernel test robot <lkp@...el.com>
To: Xi Ruoyao <xry111@...111.site>, "Jason A. Donenfeld" <Jason@...c4.com>,
Thomas Weißschuh <thomas.weissschuh@...utronix.de>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>, Guo Ren <guoren@...nel.org>
Cc: llvm@...ts.linux.dev, oe-kbuild-all@...ts.linux.dev,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
Xi Ruoyao <xry111@...111.site>
Subject: Re: [PATCH] RISC-V: vDSO: Wire up getrandom() vDSO implementation
Hi Xi,
kernel test robot noticed the following build errors:
[auto build test ERROR on crng-random/master]
[also build test ERROR on shuah-kselftest/next shuah-kselftest/fixes linus/master v6.14-rc4 next-20250228]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Xi-Ruoyao/RISC-V-vDSO-Wire-up-getrandom-vDSO-implementation/20250224-203232
base: https://git.kernel.org/pub/scm/linux/kernel/git/crng/random.git master
patch link: https://lore.kernel.org/r/20250224122541.65045-1-xry111%40xry111.site
patch subject: [PATCH] RISC-V: vDSO: Wire up getrandom() vDSO implementation
config: riscv-randconfig-001-20250302 (https://download.01.org/0day-ci/archive/20250302/202503020317.POudjwvT-lkp@intel.com/config)
compiler: clang version 21.0.0git (https://github.com/llvm/llvm-project 14170b16028c087ca154878f5ed93d3089a965c6)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250302/202503020317.POudjwvT-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@...el.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202503020317.POudjwvT-lkp@intel.com/
All errors (new ones prefixed by >>):
>> arch/riscv/kernel/vdso/vgetrandom-chacha.S:92:2: error: instruction requires the following: RV64I Base Instruction Set
ld t2, (a2)
^
>> arch/riscv/kernel/vdso/vgetrandom-chacha.S:118:15: error: immediate must be an integer in the range [0, 31]
srli a6, t2, 32
^
>> <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
addw s0, s0, s4
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:127:2: note: while in macro instantiation
OP_4REG addw s0, s1, s2, s3, s4, s5, s6, s7
^
<instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
addw s1, s1, s5
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:127:2: note: while in macro instantiation
OP_4REG addw s0, s1, s2, s3, s4, s5, s6, s7
^
<instantiation>:3:2: error: instruction requires the following: RV64I Base Instruction Set
addw s2, s2, s6
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:127:2: note: while in macro instantiation
OP_4REG addw s0, s1, s2, s3, s4, s5, s6, s7
^
<instantiation>:4:2: error: instruction requires the following: RV64I Base Instruction Set
addw s3, s3, s7
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:127:2: note: while in macro instantiation
OP_4REG addw s0, s1, s2, s3, s4, s5, s6, s7
^
>> <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
slliw t0, a5, 32 - 16
^
<instantiation>:1:1: note: while in macro instantiation
ROTRI a5, a5, 16
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:129:2: note: while in macro instantiation
OP_4REG ROTRI a5, a6, a7, t1, 16, 16, 16, 16
^
<instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
srliw a5, a5, 16
^
<instantiation>:1:1: note: while in macro instantiation
ROTRI a5, a5, 16
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:129:2: note: while in macro instantiation
OP_4REG ROTRI a5, a6, a7, t1, 16, 16, 16, 16
^
>> <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
slliw t0, a6, 32 - 16
^
<instantiation>:2:2: note: while in macro instantiation
ROTRI a6, a6, 16
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:129:2: note: while in macro instantiation
OP_4REG ROTRI a5, a6, a7, t1, 16, 16, 16, 16
^
<instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
srliw a6, a6, 16
^
<instantiation>:2:2: note: while in macro instantiation
ROTRI a6, a6, 16
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:129:2: note: while in macro instantiation
OP_4REG ROTRI a5, a6, a7, t1, 16, 16, 16, 16
^
>> <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
slliw t0, a7, 32 - 16
^
<instantiation>:3:2: note: while in macro instantiation
ROTRI a7, a7, 16
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:129:2: note: while in macro instantiation
OP_4REG ROTRI a5, a6, a7, t1, 16, 16, 16, 16
^
<instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
srliw a7, a7, 16
^
<instantiation>:3:2: note: while in macro instantiation
ROTRI a7, a7, 16
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:129:2: note: while in macro instantiation
OP_4REG ROTRI a5, a6, a7, t1, 16, 16, 16, 16
^
>> <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
slliw t0, t1, 32 - 16
^
<instantiation>:4:2: note: while in macro instantiation
ROTRI t1, t1, 16
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:129:2: note: while in macro instantiation
OP_4REG ROTRI a5, a6, a7, t1, 16, 16, 16, 16
^
<instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
srliw t1, t1, 16
^
<instantiation>:4:2: note: while in macro instantiation
ROTRI t1, t1, 16
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:129:2: note: while in macro instantiation
OP_4REG ROTRI a5, a6, a7, t1, 16, 16, 16, 16
^
>> <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
addw s8, s8, a5
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:131:2: note: while in macro instantiation
OP_4REG addw s8, s9, s10, s11, a5, a6, a7, t1
^
<instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
addw s9, s9, a6
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:131:2: note: while in macro instantiation
OP_4REG addw s8, s9, s10, s11, a5, a6, a7, t1
^
<instantiation>:3:2: error: instruction requires the following: RV64I Base Instruction Set
addw s10, s10, a7
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:131:2: note: while in macro instantiation
OP_4REG addw s8, s9, s10, s11, a5, a6, a7, t1
^
<instantiation>:4:2: error: instruction requires the following: RV64I Base Instruction Set
addw s11, s11, t1
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:131:2: note: while in macro instantiation
OP_4REG addw s8, s9, s10, s11, a5, a6, a7, t1
^
>> <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
slliw t0, s4, 32 - 20
^
<instantiation>:1:1: note: while in macro instantiation
ROTRI s4, s4, 20
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:133:2: note: while in macro instantiation
OP_4REG ROTRI s4, s5, s6, s7, 20, 20, 20, 20
^
<instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
srliw s4, s4, 20
^
<instantiation>:1:1: note: while in macro instantiation
ROTRI s4, s4, 20
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:133:2: note: while in macro instantiation
OP_4REG ROTRI s4, s5, s6, s7, 20, 20, 20, 20
^
>> <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
slliw t0, s5, 32 - 20
^
<instantiation>:2:2: note: while in macro instantiation
ROTRI s5, s5, 20
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:133:2: note: while in macro instantiation
OP_4REG ROTRI s4, s5, s6, s7, 20, 20, 20, 20
^
<instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
srliw s5, s5, 20
^
<instantiation>:2:2: note: while in macro instantiation
ROTRI s5, s5, 20
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:133:2: note: while in macro instantiation
OP_4REG ROTRI s4, s5, s6, s7, 20, 20, 20, 20
^
>> <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
slliw t0, s6, 32 - 20
^
<instantiation>:3:2: note: while in macro instantiation
ROTRI s6, s6, 20
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:133:2: note: while in macro instantiation
OP_4REG ROTRI s4, s5, s6, s7, 20, 20, 20, 20
^
<instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
srliw s6, s6, 20
^
<instantiation>:3:2: note: while in macro instantiation
ROTRI s6, s6, 20
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:133:2: note: while in macro instantiation
OP_4REG ROTRI s4, s5, s6, s7, 20, 20, 20, 20
^
>> <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
slliw t0, s7, 32 - 20
^
<instantiation>:4:2: note: while in macro instantiation
ROTRI s7, s7, 20
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:133:2: note: while in macro instantiation
OP_4REG ROTRI s4, s5, s6, s7, 20, 20, 20, 20
^
<instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
srliw s7, s7, 20
^
<instantiation>:4:2: note: while in macro instantiation
ROTRI s7, s7, 20
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:133:2: note: while in macro instantiation
OP_4REG ROTRI s4, s5, s6, s7, 20, 20, 20, 20
^
>> <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
addw s0, s0, s4
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:135:2: note: while in macro instantiation
OP_4REG addw s0, s1, s2, s3, s4, s5, s6, s7
^
<instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
addw s1, s1, s5
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:135:2: note: while in macro instantiation
OP_4REG addw s0, s1, s2, s3, s4, s5, s6, s7
^
<instantiation>:3:2: error: instruction requires the following: RV64I Base Instruction Set
addw s2, s2, s6
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:135:2: note: while in macro instantiation
OP_4REG addw s0, s1, s2, s3, s4, s5, s6, s7
^
<instantiation>:4:2: error: instruction requires the following: RV64I Base Instruction Set
addw s3, s3, s7
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:135:2: note: while in macro instantiation
OP_4REG addw s0, s1, s2, s3, s4, s5, s6, s7
^
>> <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
slliw t0, a5, 32 - 24
^
<instantiation>:1:1: note: while in macro instantiation
ROTRI a5, a5, 24
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:137:2: note: while in macro instantiation
OP_4REG ROTRI a5, a6, a7, t1, 24, 24, 24, 24
^
<instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
srliw a5, a5, 24
^
<instantiation>:1:1: note: while in macro instantiation
ROTRI a5, a5, 24
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:137:2: note: while in macro instantiation
OP_4REG ROTRI a5, a6, a7, t1, 24, 24, 24, 24
^
>> <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
slliw t0, a6, 32 - 24
^
<instantiation>:2:2: note: while in macro instantiation
ROTRI a6, a6, 24
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:137:2: note: while in macro instantiation
OP_4REG ROTRI a5, a6, a7, t1, 24, 24, 24, 24
^
<instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
srliw a6, a6, 24
^
<instantiation>:2:2: note: while in macro instantiation
ROTRI a6, a6, 24
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:137:2: note: while in macro instantiation
OP_4REG ROTRI a5, a6, a7, t1, 24, 24, 24, 24
^
>> <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
slliw t0, a7, 32 - 24
^
<instantiation>:3:2: note: while in macro instantiation
ROTRI a7, a7, 24
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:137:2: note: while in macro instantiation
OP_4REG ROTRI a5, a6, a7, t1, 24, 24, 24, 24
^
<instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
srliw a7, a7, 24
^
<instantiation>:3:2: note: while in macro instantiation
ROTRI a7, a7, 24
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:137:2: note: while in macro instantiation
OP_4REG ROTRI a5, a6, a7, t1, 24, 24, 24, 24
^
>> <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
slliw t0, t1, 32 - 24
^
<instantiation>:4:2: note: while in macro instantiation
ROTRI t1, t1, 24
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:137:2: note: while in macro instantiation
OP_4REG ROTRI a5, a6, a7, t1, 24, 24, 24, 24
^
<instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
srliw t1, t1, 24
^
<instantiation>:4:2: note: while in macro instantiation
ROTRI t1, t1, 24
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:137:2: note: while in macro instantiation
OP_4REG ROTRI a5, a6, a7, t1, 24, 24, 24, 24
^
>> <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
addw s8, s8, a5
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:139:2: note: while in macro instantiation
OP_4REG addw s8, s9, s10, s11, a5, a6, a7, t1
^
<instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
addw s9, s9, a6
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:139:2: note: while in macro instantiation
OP_4REG addw s8, s9, s10, s11, a5, a6, a7, t1
^
<instantiation>:3:2: error: instruction requires the following: RV64I Base Instruction Set
addw s10, s10, a7
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:139:2: note: while in macro instantiation
OP_4REG addw s8, s9, s10, s11, a5, a6, a7, t1
^
<instantiation>:4:2: error: instruction requires the following: RV64I Base Instruction Set
addw s11, s11, t1
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:139:2: note: while in macro instantiation
OP_4REG addw s8, s9, s10, s11, a5, a6, a7, t1
^
>> <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
slliw t0, s4, 32 - 25
^
<instantiation>:1:1: note: while in macro instantiation
ROTRI s4, s4, 25
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:141:2: note: while in macro instantiation
OP_4REG ROTRI s4, s5, s6, s7, 25, 25, 25, 25
^
<instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
srliw s4, s4, 25
^
<instantiation>:1:1: note: while in macro instantiation
ROTRI s4, s4, 25
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:141:2: note: while in macro instantiation
OP_4REG ROTRI s4, s5, s6, s7, 25, 25, 25, 25
^
>> <instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
slliw t0, s5, 32 - 25
^
<instantiation>:2:2: note: while in macro instantiation
ROTRI s5, s5, 25
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:141:2: note: while in macro instantiation
OP_4REG ROTRI s4, s5, s6, s7, 25, 25, 25, 25
^
<instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
srliw s5, s5, 25
^
<instantiation>:2:2: note: while in macro instantiation
ROTRI s5, s5, 25
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:141:2: note: while in macro instantiation
OP_4REG ROTRI s4, s5, s6, s7, 25, 25, 25, 25
^
<instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
slliw t0, s6, 32 - 25
^
<instantiation>:3:2: note: while in macro instantiation
ROTRI s6, s6, 25
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:141:2: note: while in macro instantiation
OP_4REG ROTRI s4, s5, s6, s7, 25, 25, 25, 25
^
<instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
srliw s6, s6, 25
^
<instantiation>:3:2: note: while in macro instantiation
ROTRI s6, s6, 25
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:141:2: note: while in macro instantiation
OP_4REG ROTRI s4, s5, s6, s7, 25, 25, 25, 25
^
<instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
slliw t0, s7, 32 - 25
^
<instantiation>:4:2: note: while in macro instantiation
ROTRI s7, s7, 25
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:141:2: note: while in macro instantiation
OP_4REG ROTRI s4, s5, s6, s7, 25, 25, 25, 25
^
<instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
srliw s7, s7, 25
^
<instantiation>:4:2: note: while in macro instantiation
ROTRI s7, s7, 25
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:141:2: note: while in macro instantiation
OP_4REG ROTRI s4, s5, s6, s7, 25, 25, 25, 25
^
<instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
addw s0, s0, s5
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:144:2: note: while in macro instantiation
OP_4REG addw s0, s1, s2, s3, s5, s6, s7, s4
^
<instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
addw s1, s1, s6
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:144:2: note: while in macro instantiation
OP_4REG addw s0, s1, s2, s3, s5, s6, s7, s4
^
<instantiation>:3:2: error: instruction requires the following: RV64I Base Instruction Set
addw s2, s2, s7
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:144:2: note: while in macro instantiation
OP_4REG addw s0, s1, s2, s3, s5, s6, s7, s4
^
<instantiation>:4:2: error: instruction requires the following: RV64I Base Instruction Set
addw s3, s3, s4
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:144:2: note: while in macro instantiation
OP_4REG addw s0, s1, s2, s3, s5, s6, s7, s4
^
<instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
slliw t0, t1, 32 - 16
^
<instantiation>:1:1: note: while in macro instantiation
ROTRI t1, t1, 16
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:146:2: note: while in macro instantiation
OP_4REG ROTRI t1, a5, a6, a7, 16, 16, 16, 16
^
<instantiation>:2:2: error: instruction requires the following: RV64I Base Instruction Set
srliw t1, t1, 16
^
<instantiation>:1:1: note: while in macro instantiation
ROTRI t1, t1, 16
^
arch/riscv/kernel/vdso/vgetrandom-chacha.S:146:2: note: while in macro instantiation
OP_4REG ROTRI t1, a5, a6, a7, 16, 16, 16, 16
^
<instantiation>:1:1: error: instruction requires the following: RV64I Base Instruction Set
slliw t0, a5, 32 - 16
^
<instantiation>:2:2: note: while in macro instantiation
ROTRI a5, a5, 16
vim +92 arch/riscv/kernel/vdso/vgetrandom-chacha.S
77
78 addi sp, sp, -12*SZREG
79 REG_S s0, (sp)
80 REG_S s1, SZREG(sp)
81 REG_S s2, 2*SZREG(sp)
82 REG_S s3, 3*SZREG(sp)
83 REG_S s4, 4*SZREG(sp)
84 REG_S s5, 5*SZREG(sp)
85 REG_S s6, 6*SZREG(sp)
86 REG_S s7, 7*SZREG(sp)
87 REG_S s8, 8*SZREG(sp)
88 REG_S s9, 9*SZREG(sp)
89 REG_S s10, 10*SZREG(sp)
90 REG_S s11, 11*SZREG(sp)
91
> 92 ld cnt, (counter)
93
94 li copy0, 0x61707865
95 li copy1, 0x3320646e
96 li copy2, 0x79622d32
97 li copy3, 0x6b206574
98
99 .Lblock:
100 /* state[0,1,2,3] = "expand 32-byte k" */
101 mv state0, copy0
102 mv state1, copy1
103 mv state2, copy2
104 mv state3, copy3
105
106 /* state[4,5,..,11] = key */
107 lw state4, (key)
108 lw state5, 4(key)
109 lw state6, 8(key)
110 lw state7, 12(key)
111 lw state8, 16(key)
112 lw state9, 20(key)
113 lw state10, 24(key)
114 lw state11, 28(key)
115
116 /* state[12,13] = counter */
117 mv state12, cnt
> 118 srli state13, cnt, 32
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
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