linux-kernel - Re: [PATCH v7 04/43] drm/mediatek: mtk_dpi: Move pixel clock setting flow to function

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Message-ID: <CAAOTY__DqCA3+-nsi7+svqHTbjdpTU5+8yDqWwNMnU8V=euQbQ@mail.gmail.com>
Date: Sun, 2 Mar 2025 19:08:08 +0800
From: Chun-Kuang Hu <chunkuang.hu@...nel.org>
To: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
Cc: chunkuang.hu@...nel.org, p.zabel@...gutronix.de, airlied@...il.com, 
	simona@...ll.ch, maarten.lankhorst@...ux.intel.com, mripard@...nel.org, 
	tzimmermann@...e.de, robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org, 
	matthias.bgg@...il.com, ck.hu@...iatek.com, jitao.shi@...iatek.com, 
	jie.qiu@...iatek.com, junzhi.zhao@...iatek.com, 
	dri-devel@...ts.freedesktop.org, linux-mediatek@...ts.infradead.org, 
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, 
	linux-arm-kernel@...ts.infradead.org, kernel@...labora.com, 
	dmitry.baryshkov@...aro.org, lewis.liao@...iatek.com, 
	ives.chenjh@...iatek.com, tommyyl.chen@...iatek.com, 
	jason-jh.lin@...iatek.com
Subject: Re: [PATCH v7 04/43] drm/mediatek: mtk_dpi: Move pixel clock setting
 flow to function

Hi, Angelo:

AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com> 於
2025年2月17日 週一 下午11:49寫道：
>
> In preparation for adding support for the DPI IP found in MT8195
> and in MT8188 used for HDMI, move the code flow for calculation
> and setting of the DPI pixel clock to a separate function called
> mtk_dpi_set_pixel_clk().
>
> This was done because, on those platforms, the DPI instance that
> is used for HDMI will get its pixel clock from the HDMI clock,
> hence it is not necessary, nor desirable, to calculate or set
> the pixel clock in DPI.

After fix conflicts, applied to mediatek-drm-next [1], thanks.

[1] https://web.git.kernel.org/pub/scm/linux/kernel/git/chunkuang.hu/linux.git/log/?h=mediatek-drm-next

Regards,
Chun-Kuang.

>
> Reviewed-by: CK Hu <ck.hu@...iatek.com>
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_dpi.c | 43 +++++++++++++++++-------------
>  1 file changed, 24 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
> index 41fdc193891a..59c2e4f32a61 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dpi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
> @@ -537,26 +537,17 @@ static unsigned int mtk_dpi_calculate_factor(struct mtk_dpi *dpi, int mode_clk)
>         return dpi_factor[dpi->conf->num_dpi_factor - 1].factor;
>  }
>
> -static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
> -                                   struct drm_display_mode *mode)
> +static void mtk_dpi_set_pixel_clk(struct mtk_dpi *dpi, struct videomode *vm, int mode_clk)
>  {
> -       struct mtk_dpi_polarities dpi_pol;
> -       struct mtk_dpi_sync_param hsync;
> -       struct mtk_dpi_sync_param vsync_lodd = { 0 };
> -       struct mtk_dpi_sync_param vsync_leven = { 0 };
> -       struct mtk_dpi_sync_param vsync_rodd = { 0 };
> -       struct mtk_dpi_sync_param vsync_reven = { 0 };
> -       struct videomode vm = { 0 };
>         unsigned long pll_rate;
>         unsigned int factor;
>
>         /* let pll_rate can fix the valid range of tvdpll (1G~2GHz) */
>         factor = mtk_dpi_calculate_factor(dpi, mode_clk);
> -       drm_display_mode_to_videomode(mode, &vm);
> -       pll_rate = vm.pixelclock * factor;
> +       pll_rate = vm->pixelclock * factor;
>
>         dev_dbg(dpi->dev, "Want PLL %lu Hz, pixel clock %lu Hz\n",
> -               pll_rate, vm.pixelclock);
> +               pll_rate, vm->pixelclock);
>
>         clk_set_rate(dpi->tvd_clk, pll_rate);
>         pll_rate = clk_get_rate(dpi->tvd_clk);
> @@ -566,20 +557,34 @@ static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
>          * pixels for each iteration: divide the clock by this number and
>          * adjust the display porches accordingly.
>          */
> -       vm.pixelclock = pll_rate / factor;
> -       vm.pixelclock /= dpi->conf->pixels_per_iter;
> +       vm->pixelclock = pll_rate / factor;
> +       vm->pixelclock /= dpi->conf->pixels_per_iter;
>
>         if ((dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_LE) ||
>             (dpi->output_fmt == MEDIA_BUS_FMT_RGB888_2X12_BE))
> -               clk_set_rate(dpi->pixel_clk, vm.pixelclock * 2);
> +               clk_set_rate(dpi->pixel_clk, vm->pixelclock * 2);
>         else
> -               clk_set_rate(dpi->pixel_clk, vm.pixelclock);
> +               clk_set_rate(dpi->pixel_clk, vm->pixelclock);
>
> -
> -       vm.pixelclock = clk_get_rate(dpi->pixel_clk);
> +       vm->pixelclock = clk_get_rate(dpi->pixel_clk);
>
>         dev_dbg(dpi->dev, "Got  PLL %lu Hz, pixel clock %lu Hz\n",
> -               pll_rate, vm.pixelclock);
> +               pll_rate, vm->pixelclock);
> +}
> +
> +static int mtk_dpi_set_display_mode(struct mtk_dpi *dpi,
> +                                   struct drm_display_mode *mode)
> +{
> +       struct mtk_dpi_polarities dpi_pol;
> +       struct mtk_dpi_sync_param hsync;
> +       struct mtk_dpi_sync_param vsync_lodd = { 0 };
> +       struct mtk_dpi_sync_param vsync_leven = { 0 };
> +       struct mtk_dpi_sync_param vsync_rodd = { 0 };
> +       struct mtk_dpi_sync_param vsync_reven = { 0 };
> +       struct videomode vm = { 0 };
> +
> +       drm_display_mode_to_videomode(mode, &vm);
> +       mtk_dpi_set_pixel_clk(dpi, &vm, mode->clock);
>
>         dpi_pol.ck_pol = MTK_DPI_POLARITY_FALLING;
>         dpi_pol.de_pol = MTK_DPI_POLARITY_RISING;
> --
> 2.48.1
>