linux-kernel - Re: [PATCH 2/2] dt-bindings: net: dsa: qca8k: add internal-PHY-to-PHY CPU link example

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Message-ID: <f7ac97f4-7677-402d-99f1-ae82709a3549@lunn.ch>
Date: Tue, 4 Mar 2025 15:11:32 +0100
From: Andrew Lunn <andrew@...n.ch>
To: H ZY <hzyitc@...look.com>
Cc: "olteanv@...il.com" <olteanv@...il.com>,
	"davem@...emloft.net" <davem@...emloft.net>,
	"edumazet@...gle.com" <edumazet@...gle.com>,
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	"robh@...nel.org" <robh@...nel.org>,
	"krzk+dt@...nel.org" <krzk+dt@...nel.org>,
	"conor+dt@...nel.org" <conor+dt@...nel.org>,
	"rmk+kernel@...linux.org.uk" <rmk+kernel@...linux.org.uk>,
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	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
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Subject: Re: [PATCH 2/2] dt-bindings: net: dsa: qca8k: add
 internal-PHY-to-PHY CPU link example

> (Port0 and Port6). Could I just keep this or should I need to add a new
> case ?

The existing examples are probably sufficient. Just check the text to
make sure it does not limit it to ports 0 and 6.

> > So is this actually internally? Or do you have a IPQ50xx SoC connected
> > to a qca8337 switch, with copper traces on a PCB? If so, it is not
> > internal.
> 
> The "internal" is used to describe the localcation of PHY not the link.
> In current code, qca8k has supported to use a external PHY to do a
> PHY-to-PHY link (Port0 and Port6). This patch make the internal PHYs
> support it too (Port1-5).
> 
> The followiing topology is existed in most IPQ50xx-based router:
>     _______________________         _______________________
>    |        IPQ5018        |       |        QCA8337        |
>    | +------+   +--------+ |       | +--------+   +------+ |
>    | | MAC0 |---| GE Phy |-+--MDI--+-|  Phy4  |---| MAC5 | |
>    | +------+   +--------+ |       | +--------+   +------+ |
>    | +------+   +--------+ |       | +--------+   +------+ |
>    | | MAC1 |---| Uniphy |-+-SGMII-+-| SerDes |---| MAC0 | |
>    | +------+   +--------+ |       | +--------+   +------+ |
>    |_______________________|       |_______________________|

So logically, it does not matter if the PHY is internal or
external. The patch would be the same. I've even see setups where the
SGMII link would have a PHY, then a connection to a daughter board,
and then a PHY back to SGMII before connecting to the switch. Running
Ethernet over the connector is easier than SERDES lines.

So i would probably drop the word internal from this discussion,
unless it is really relevant.

	Andrew