linux-kernel - Re: [Intel-wired-lan] [PATCH] e1000e: Link flap workaround option for false IRP events

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Message-ID: <eb5b93b5-ca90-4287-b6b5-17825d79e6ea@lunn.ch>
Date: Tue, 4 Mar 2025 23:24:05 +0100
From: Andrew Lunn <andrew@...n.ch>
To: Mark Pearson <mpearson-lenovo@...ebb.ca>
Cc: Vitaly Lifshits <vitaly.lifshits@...el.com>, anthony.l.nguyen@...el.com,
	przemyslaw.kitszel@...el.com, andrew+netdev@...n.ch,
	davem@...emloft.net, edumazet@...gle.com, kuba@...nel.org,
	pabeni@...hat.com, intel-wired-lan@...ts.osuosl.org,
	netdev@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [Intel-wired-lan] [PATCH] e1000e: Link flap workaround option
 for false IRP events

> > I suggest to try replacing the register read for a short delay or 
> > reading the PHY STATUS register instead.
> >
> 
> Ack - we'll try that, and collect some other debug registers in the process.
> Will update with findings - this may take a while :)

Please be careful with which register you choice. Because the link
status bit in BMSR is latching, you should not be reading it and
discarding the result.

Reading register 2 or 3 should be totally safe.

Another thing to keep in mind, you cannot unconditionally read a paged
register in this particular PHY, because the e1000e is used with a
number of different PHYs. That register does not exist in other PHYs,
and the action of selecting the page performs a register write, which
for some other PHY could be destructive. So i would suggest you keep
to registers defined in 802.3 C22.

	Andrew