linux-kernel - Re: [PATCH] reset: rzg2l-usbphy-ctrl: Correct reset status check

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <CA+V-a8t8o92C4OYac4xXxS7quieNZWWPJxoT2dsrZ0M0AmWW-A@mail.gmail.com>
Date: Tue, 4 Mar 2025 07:41:04 +0000
From: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
To: Biju Das <biju.das.jz@...renesas.com>
Cc: Philipp Zabel <p.zabel@...gutronix.de>, 
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, 
	"linux-renesas-soc@...r.kernel.org" <linux-renesas-soc@...r.kernel.org>, 
	Fabrizio Castro <fabrizio.castro.jz@...esas.com>, 
	Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...renesas.com>, 
	"stable@...r.kernel.org" <stable@...r.kernel.org>
Subject: Re: [PATCH] reset: rzg2l-usbphy-ctrl: Correct reset status check

Hi Biju,

Thank you for the review.

On Tue, Mar 4, 2025 at 6:43 AM Biju Das <biju.das.jz@...renesas.com> wrote:
>
> Hi Prabhakar,
>
> Thanks for the patch.
>
> > -----Original Message-----
> > From: Prabhakar <prabhakar.csengg@...il.com>
> > Sent: 03 March 2025 19:09
> > Subject: [PATCH] reset: rzg2l-usbphy-ctrl: Correct reset status check
> >
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> >
> > Ensure the reset status check explicitly evaluates whether all bits in `port_mask` are set. Replace
> > the double negation (`!!`) with an equality check to prevent incorrect interpretation of partial bit
> > matches as an asserted reset.
> >
> > Fixes: bee08559701f ("reset: renesas: Add RZ/G2L usbphy control driver")
> > Cc: stable@...r.kernel.org
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > ---
> >  drivers/reset/reset-rzg2l-usbphy-ctrl.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/reset/reset-rzg2l-usbphy-ctrl.c b/drivers/reset/reset-rzg2l-usbphy-ctrl.c
> > index 8a7f167e405e..6451f621e862 100644
> > --- a/drivers/reset/reset-rzg2l-usbphy-ctrl.c
> > +++ b/drivers/reset/reset-rzg2l-usbphy-ctrl.c
> > @@ -88,7 +88,7 @@ static int rzg2l_usbphy_ctrl_status(struct reset_controller_dev *rcdev,
> >
> >       port_mask = id ? PHY_RESET_PORT2 : PHY_RESET_PORT1;
> >
> > -     return !!(readl(priv->base + RESET) & port_mask);
> > +     return (readl(priv->base + RESET) & port_mask) == port_mask;
>
>
> As per the hardware manual, these status bit is valid only when
> Only when sel_pxreset=1.
>
> If sel_pxreset=0, we are reporting invalid status to the caller.
>
> Maybe we should check sel_pxreset while setting it and read it back to
> Ensure that it is set to 1 and in this function just check for
> phyrst_x bit for reporting status
>
Ok, I will update it as above and send a v2.

Cheers,
Prabhakar