linux-kernel - Re: [PATCH v1 00/40] x86: Leaf 0x2 and leaf 0x4 refactorings

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Message-ID: <Z8bI1JwDDI3JhpxP@gmail.com>
Date: Tue, 4 Mar 2025 10:33:08 +0100
From: Ingo Molnar <mingo@...nel.org>
To: "Ahmed S. Darwish" <darwi@...utronix.de>
Cc: Borislav Petkov <bp@...en8.de>, Ingo Molnar <mingo@...hat.com>,
	Dave Hansen <dave.hansen@...ux.intel.com>,
	Thomas Gleixner <tglx@...utronix.de>,
	John Ogness <john.ogness@...utronix.de>,
	"H. Peter Anvin" <hpa@...or.com>,
	Andrew Cooper <andrew.cooper3@...rix.com>, x86@...nel.org,
	x86-cpuid@...ts.linux.dev, LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v1 00/40] x86: Leaf 0x2 and leaf 0x4 refactorings


* Ahmed S. Darwish <darwi@...utronix.de> wrote:

> Ahmed S. Darwish (33):
>   x86/cacheinfo: Validate cpuid leaf 0x2 EDX output
>   x86/cpu: Validate cpuid leaf 0x2 EDX output
>   x86/cpu: Properly parse leaf 0x2 TLB descriptor 0x63
>   x86/cpuid: Include linux/build_bug.h
>   x86/cpu: Remove unnecessary headers and reorder the rest
>   x86/cpu: Use max() for leaf 0x2 TLB descriptors parsing
>   x86/cpu: Simplify TLB entry count storage
>   x86/cpu: Remove leaf 0x2 parsing loop and add helpers
>   x86/cacheinfo: Remove unnecessary headers and reorder the rest
>   x86/cacheinfo: Use cpuid leaf 0x2 parsing helpers
>   x86/cacheinfo: Constify _cpuid4_info_regs instances
>   x86/cacheinfo: Align ci_info_init() assignment expressions
>   x86/cacheinfo: Standardize _cpuid4_info_regs instance naming
>   x86: treewide: Introduce x86_vendor_amd_or_hygon()
>   x86/cacheinfo: Consolidate AMD/Hygon leaf 0x8000001d calls
>   x86/cacheinfo: Separate amd_northbridge from _cpuid4_info_regs
>   x86/cacheinfo: Move AMD cache_disable_0/1 handling to separate file
>   x86/cacheinfo: Use sysfs_emit() for sysfs attributes show()
>   x86/cacheinfo: Separate Intel and AMD leaf 0x4 code paths
>   x86/cacheinfo: Rename _cpuid4_info_regs to _cpuid4_info
>   x86/cacheinfo: Clarify type markers for leaf 0x2 cache descriptors
>   x86/cacheinfo: Use enums for cache descriptor types
>   x86/cpu: Use enums for TLB descriptor types
>   sizes.h: Cover all possible x86 cpu cache sizes
>   x86/cacheinfo: Use consolidated leaf 0x2 descriptor table
>   x86/cpu: Use consolidated leaf 0x2 descriptor table
>   x86/cacheinfo: Separate leaf 0x2 handling and post-processing logic
>   x86/cacheinfo: Separate intel leaf 0x4 handling
>   x86/cacheinfo: Extract out cache level topology ID calculation
>   x86/cacheinfo: Extract out cache self-snoop checks
>   x86/cacheinfo: Relocate leaf 0x4 cache_type mapping
>   x86/cacheinfo: Introduce amd_hygon_cpu_has_l3_cache()
>   x86/cacheinfo: Apply maintainer-tip coding style fixes

Meta spelling comments for the entire series:

Please capitalize acronyms and names consistently in titles, changelogs 
and comments alike:

 s/cpu
  /CPU

 s/intel
  /Intel

When referring to headers, please write out their canonical names where 
appropriate - for example:

   - x86/cpuid: Include linux/build_bug.h
   + x86/cpuid: Include <linux/build_bug.h>

Thanks,

	Ingo