Message-ID: <0b8f71cf-03ee-4b5f-94ba-92811fccb541@gmail.com>
Date: Tue, 4 Mar 2025 12:37:27 +0200
From: Ivaylo Ivanov <ivo.ivanov.ivanov1@...il.com>
To: Krzysztof Kozlowski <krzk@...nel.org>
Cc: Vinod Koul <vkoul@...nel.org>, Kishon Vijay Abraham I
 <kishon@...nel.org>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
 <conor+dt@...nel.org>, Alim Akhtar <alim.akhtar@...sung.com>,
 Philipp Zabel <p.zabel@...gutronix.de>, Abel Vesa <abel.vesa@...aro.org>,
 linux-arm-msm@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
 linux-samsung-soc@...r.kernel.org, linux-phy@...ts.infradead.org,
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 3/8] dt-bindings: phy: add
 samsung,exynos2200-usbcon-phy schema file

On 3/4/25 12:03, Krzysztof Kozlowski wrote:
> On 04/03/2025 10:09, Ivaylo Ivanov wrote:
>> On 3/4/25 09:21, Krzysztof Kozlowski wrote:
>>> On 03/03/2025 18:18, Ivaylo Ivanov wrote:
>>>> On 3/3/25 09:24, Krzysztof Kozlowski wrote:
>>>>> On 02/03/2025 10:16, Ivaylo Ivanov wrote:
>>>>>> On 2/25/25 10:11, Krzysztof Kozlowski wrote:
>>>>>>> On 24/02/2025 11:48, Ivaylo Ivanov wrote:
>>>>>>>> On 2/24/25 10:56, Krzysztof Kozlowski wrote:
>>>>>>>>> On Sun, Feb 23, 2025 at 02:22:22PM +0200, Ivaylo Ivanov wrote:
>>>>>>>>>> The Exynos2200 SoC has a USB controller PHY, which acts as an
>>>>>>>>>> intermediary between a USB controller (typically DWC3) and other PHYs
>>>>>>>>>> (UTMI, PIPE3). Add a dt-binding schema for it.
>>>>>>>>>>
>>>>>>>>>> Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@...il.com>
>>>>>>>>>> ---
>>>>>>>>>>  .../phy/samsung,exynos2200-usbcon-phy.yaml    | 76 +++++++++++++++++++
>>>>>>>>>>  1 file changed, 76 insertions(+)
>>>>>>>>>>  create mode 100644 Documentation/devicetree/bindings/phy/samsung,exynos2200-usbcon-phy.yaml
>>>>>>>>> You have undocumented dependencies which prevent merging this file.
>>>>>>>>> First, dependencies have to be clearly expressed.
>>>>>>>> They are, in the cover letter.
>>>>>>> Where? I read it twice. Dependencies is the most important thing and
>>>>>>> should scream at beginning of the cover letter, so if you bury them
>>>>>>> somewhere deep it also would not matter - just like they were missing.
>>>>>>>
>>>>>>>>> Second, you should
>>>>>>>>> rather decouple the code from header dependencies, otherwise this cannot
>>>>>>>>> be merged for current release (just use clocks with long names, without IDs).
>>>>>>>> Sure
>>>>>>>>>> diff --git a/Documentation/devicetree/bindings/phy/samsung,exynos2200-usbcon-phy.yaml b/Documentation/devicetree/bindings/phy/samsung,exynos2200-usbcon-phy.yaml
>>>>>>>>>> new file mode 100644
>>>>>>>>>> index 000000000..7d879ec8b
>>>>>>>>>> --- /dev/null
>>>>>>>>>> +++ b/Documentation/devicetree/bindings/phy/samsung,exynos2200-usbcon-phy.yaml
>>>>>>>>>> @@ -0,0 +1,76 @@
>>>>>>>>>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>>>>>>>>>> +%YAML 1.2
>>>>>>>>>> +---
>>>>>>>>>> +$id: http://devicetree.org/schemas/phy/samsung,exynos2200-usbcon-phy.yaml#
>>>>>>>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>>>>>>>> +
>>>>>>>>>> +title: Exynos2200 USB controller PHY
>>>>>>>>>> +
>>>>>>>>>> +maintainers:
>>>>>>>>>> +  - Ivaylo Ivanov <ivo.ivanov.ivanov1@...il.com>
>>>>>>>>>> +
>>>>>>>>>> +description:
>>>>>>>>>> +  Exynos2200 USB controller PHY is an intermediary between a USB controller
>>>>>>>>>> +  (typically DWC3) and other PHYs (UTMI, PIPE3).
>>>>>>>>> Isn't this the same as usbdrd phy? see: samsung,usb3-drd-phy.yaml
>>>>>>>> It's not (I think). There's a few reasons I've decided to make this separate
>>>>>>>> from the usb3-drd-phy bindings and exynos5-usbdrd driver:
>>>>>>>>
>>>>>>>> 1. This PHY does not provide UTMI and PIPE3 on its own. There's no tuning
>>>>>>> USBDRD phy does not provide UTMI and PIPE on its own either if you look
>>>>>>> at diagram - they call it phy controller.
>>>>>> Ughm. What? So in most exynos cases, there's a combination of multiple phys?
>>>>>>>> for them, and all that is needed from it is to disable HWACG, assert/
>>>>>>>> deassert reset and force bvalid/vbusvalid. After that SNPS eUSB2
>>>>>>>> initialization can be done and USB2 works. If the USBCON phy is not set
>>>>>>>> up before the eUSB2 one, the device hangs, so there is definitely a
>>>>>>>> dependancy between them. For PIPE3 we'd need to control the pipe3
>>>>>>>> attaching/deattaching and then initialize the synopsys USBDP combophy.
>>>>>>> Does it mean there is no USB DRD phy controller as before?
>>>>>>>
>>>>>>> Anyway the problem is you have DWC3 -> PHY -> PHY. Looks one phy too many.
>>>>>> So...
>>>>>>
>>>>>> DWC3 -> USBDRD (USBCON) -> PHYs?
>>>>> No, drop last phy. You just wrote the same as me - two phys, because
>>>>> usbdrd is the phy. In all existing designs there is no such controllable
>>>>> object from the point of view of operating system.
>>>> What? Per my understanding, the phy property should refer to whatever is
>>>> is connected to dwc3 UTMI. In this case it's the so-called USBDRD phy (called
>>>> usbcon in downstream). Considering that the eUSB2 IP definitely also has UTMI
>>>> that has to be connected to something, doesn't that mean we have clearly
>>> The entire point is that eUSB2 is connected to DWC3, no? That's exactly
>>> how it is done for example on Qualcomm SoC. Otherwise you claim that
>>> DWC3 controls one phy, which controls another phy which controls UTMI...
>> But where does the USBCON fit? Is it just a side controller? Why's it needed
>> in the first place? This is what I don't understand.
> I assume usbcon, so old usbdrd, is the second DWC3's phy, just like qcom
> qmpphy.

Ugh. For qcoms, does the first phy depend on qmpphy? If we pass it as the second phy,
I don't know how the linkreset will happen. We also have a usbdp phy, which I
suspect is used for SS as well since it's a combophy by Synopsys.

https://gitlab.com/Mis012/sm-s908b-linux-source-code/-/blob/s22_restored_history/drivers/phy/samsung/phy-exynos-usbdrd-eusb.c#L1579

Best regards,
Ivaylo

>
>>>> separated hardware blocks? Now, I guess one could argue that this USBCON
>>>> hardware block could be classified as a syscon. But I don't see the problem
>>>> with the current binding description, nor the modelling, as it represents
>>>> how the hardware is (unless I've gotten it completely wrong).
>>> It is the first time you use argument that it represents how the
>>> hardware is and this is what we actually disagree. It is not like that.
>>> You do not have chain of phys. Just look at any USB 3.0 DRD DWC diagram
>>> from any Samsung SoC: where would you squeeze these two phys in relation
>>> to what is called there "USB 3.0 PHY" which would be the third phy (!!!).
>> Yeah, my point was that it was different from any previous design. Now,
>> I don't know if it's actually theoretically possible to design it like so. It's
>> hard to just guess how the hardware is designed without having access
>> to die shots, documentations or even just schematics.
>>
>> Let's make it clear now, the changes your request are to document USBCON
>> in the existing exynos binding, as well as to correct all explanations of how
>> this block functions, right?
> No, not necessarily. If USBCON is entirely different device than USBDRD
> (different register layout, different features), then go ahead with a
> new binding.
>
> I was questioning your chain of PHYs and this should be investigated.
>
>
> Best regards,
> Krzysztof

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