linux-kernel - Re: [PATCH 1/3] clk: renesas: rzv2h-cpg: Move PLL access macros to source file

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Message-ID: <CAMuHMdVwVemQfrDFH48n9Csp6=KtFs5MpZ6e+wLWSnEuh2gdvg@mail.gmail.com>
Date: Wed, 5 Mar 2025 17:18:55 +0100
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Prabhakar <prabhakar.csengg@...il.com>
Cc: Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, 
	linux-renesas-soc@...r.kernel.org, linux-clk@...r.kernel.org, 
	linux-kernel@...r.kernel.org, Biju Das <biju.das.jz@...renesas.com>, 
	Fabrizio Castro <fabrizio.castro.jz@...esas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH 1/3] clk: renesas: rzv2h-cpg: Move PLL access macros to
 source file

Hi Prabhakar,

On Tue, 18 Feb 2025 at 12:44, Prabhakar <prabhakar.csengg@...il.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> Move the `PLL_CLK_ACCESS()`, `PLL_CLK1_OFFSET()`, and `PLL_CLK2_OFFSET()`
> macros from `rzv2h-cpg.h` to `rzv2h-cpg.c`, as they are not intended for
> use by SoC-specific CPG drivers.
>
> Additionally, update `PLL_CLK1_OFFSET()` and `PLL_CLK2_OFFSET()` to use
> the `FIELD_GET()` macro for better readability and simplify the
> `PLL_CLK_ACCESS()` macro.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>

Thanks for your patch!

The changes look correct to me, so
Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
but I still have some comments...

> --- a/drivers/clk/renesas/rzv2h-cpg.c
> +++ b/drivers/clk/renesas/rzv2h-cpg.c
> @@ -56,6 +56,10 @@
>
>  #define CPG_CLKSTATUS0         (0x700)
>
> +#define PLL_CLK_ACCESS(n)      (!!((n) & BIT(31)))

OK

> +#define PLL_CLK1_OFFSET(n)     FIELD_GET(GENMASK(15, 0), (n))
> +#define PLL_CLK2_OFFSET(n)     (PLL_CLK1_OFFSET(n) + (0x4))

IMO, the original versions are more readable, as they clearly show
the symmetry between encoding and decoding.

Perhaps a good alternative would be a structure with bitfields and
a PACK() macro, like is used for DDIV and SMUX?

> +
>  /**
>   * struct rzv2h_cpg_priv - Clock Pulse Generator Private Data
>   *
> diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h
> index fd8eb985c75b..81f44b94f6d5 100644
> --- a/drivers/clk/renesas/rzv2h-cpg.h
> +++ b/drivers/clk/renesas/rzv2h-cpg.h
> @@ -87,9 +87,6 @@ enum clk_types {
>
>  /* BIT(31) indicates if CLK1/2 are accessible or not */
>  #define PLL_CONF(n)            (BIT(31) | ((n) & ~GENMASK(31, 16)))
> -#define PLL_CLK_ACCESS(n)      ((n) & BIT(31) ? 1 : 0)
> -#define PLL_CLK1_OFFSET(n)     ((n) & ~GENMASK(31, 16))
> -#define PLL_CLK2_OFFSET(n)     (((n) & ~GENMASK(31, 16)) + (0x4))
>
>  #define DEF_TYPE(_name, _id, _type...) \
>         { .name = _name, .id = _id, .type = _type }

Gr{oetje,eeting}s,

                        Geert


--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds